Two independent 4-bit synchronous binary up counters in one SOIC-16, 4000-series CMOS. Each counter increments through 0-15 and presents the count on four outputs (Q0-Q3), with a clock and an enable that together allow rising- or falling-edge counting, plus an active-high reset. Because the outputs of one stage change together (synchronous), it avoids the ripple-glitch of a chain of flip-flops. Cascade the two counters for an 8-bit count, or use them separately as dividers and timers. Runs 3-18 V.

Pinout

Pin	Name	Type	Function
1	CLOCK A	input	Clock input for counter A. Counter A increments on the positive-going clock edge when ENABLE A is high, or on the negative-going enable edge when CLOCK A is held high. Minimum pulse width 200 ns @ 5 V, 100 ns @ 10 V, 70 ns @ 15 V.
2	ENABLE A	input	Enable input for counter A. Held high for positive-edge triggering by CLOCK A, or driven low-going for negative-edge triggering while CLOCK A is high. Minimum pulse width 400 ns @ 5 V, 200 ns @ 10 V, 140 ns @ 15 V.
3	Q1A	output	Counter A binary output bit 0 (LSB). Toggles once per counter increment; drives standard CMOS logic loads (IOL 0.51 mA @ VDD=5 V, VOL≤0.05 V).
4	Q2A	output	Counter A binary output bit 1. Toggles at half the Q1A rate in normal binary counting sequence.
5	Q3A	output	Counter A binary output bit 2. Toggles at one-quarter the Q1A rate in normal binary counting sequence.
6	Q4A	output	Counter A binary output bit 3 (MSB). Used as the ripple-carry source when cascading counter A into the ENABLE or CLOCK input of the next counter stage.
7	RESET A	input	Asynchronous master reset for counter A. Active-high level input; a logic-high forces Q1A-Q4A to 0. Minimum reset pulse width 250 ns @ 5 V, 110 ns @ 10 V, 80 ns @ 15 V.
8	VSS	power_in	Negative supply / ground reference. All voltages in the datasheet are referenced to this pin.
9	CLOCK B	input	Clock input for counter B. Same triggering rules and pulse-width limits as CLOCK A (positive edge with ENABLE B high, or negative-edge on ENABLE B with CLOCK B held high).
10	ENABLE B	input	Enable input for counter B. Held high for positive-edge triggering by CLOCK B, or driven low-going for negative-edge triggering while CLOCK B is high.
11	Q1B	output	Counter B binary output bit 0 (LSB). Toggles once per counter B increment.
12	Q2B	output	Counter B binary output bit 1. Toggles at half the Q1B rate.
13	Q3B	output	Counter B binary output bit 2. Toggles at one-quarter the Q1B rate.
14	Q4B	output	Counter B binary output bit 3 (MSB). Ripple-carry source when cascading counter B into another counter stage.
15	RESET B	input	Asynchronous master reset for counter B. Active-high level input; a logic-high forces Q1B-Q4B to 0.
16	VDD	power_in	Positive supply pin. Operating range 3-18 V (absolute maximum 20 V referenced to VSS). Bypass with a local 0.1 µF ceramic to VSS.

Key specifications

Parameter	Value
Type	Dual 4-bit synchronous binary counter
Counters	2 independent (0-15 each)
Outputs	Q0-Q3 per counter
Clocking	clock + enable (either edge)
Reset	active-high per counter
Logic family	4000B CMOS
Supply voltage	3-18 V
Package	SOIC-16

Ordering variants

Same part, different packaging or reel option.

CD4520BM (SOIC-16, tube)
CD4520BM96 (SOIC-16, tape & reel)

CAD (KiCad official)

Symbol: 4xxx:4520
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOIC-16 (KiCad packages3D)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (21 pp, sha256 5a70590c9c8683e3, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF