CD4098BM96 from Texas Instruments, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	CX1	passive	External timing capacitor Cx connection for MONO1. Cx is tied between pin 1 (CX1) and pin 2 (Rx·Cx). Cx can range up to 100 µF.
2	RX/CX(1)	passive	External Rx-Cx junction for MONO1. Rx (min 5 kΩ) is tied from this pin to VDD; Cx is tied between this pin and pin 1. Sets one-shot pulse width T ≈ 0.5·Rx·Cx for Cx ≥ 0.01 µF.
3	RESET(1)	input	Active-low asynchronous reset for MONO1. A low level immediately terminates the output pulse or prevents output pulses when power is turned on. Tie to VDD if unused.
4	+TR(1)	input	Leading-edge (positive) trigger input for MONO1. Used with Qbar1 connected to +TR for leading-edge non-retriggerable mode. Tie to VSS if unused.
5	-TR(1)	input	Trailing-edge (negative) trigger input for MONO1. Used with Q1 connected to -TR for trailing-edge non-retriggerable mode. Tie to VDD if unused.
6	Q1	output	Buffered true output for MONO1 one-shot pulse.
7	~Q1	output	Buffered complementary (inverted) output for MONO1.
8	VSS	power_in	Negative supply / ground reference. Terminals 1, 8, 15 are electrically connected internally through package substrate paths; VSS is the ground return for both monostables.
9	~Q2	output	Buffered complementary (inverted) output for MONO2.
10	Q2	output	Buffered true output for MONO2 one-shot pulse.
11	-TR(2)	input	Trailing-edge (negative) trigger input for MONO2. Tie to VDD if unused.
12	+TR(2)	input	Leading-edge (positive) trigger input for MONO2. Tie to VSS if unused.
13	RESET(2)	input	Active-low asynchronous reset for MONO2. A low level terminates the output pulse immediately. Tie to VDD if unused.
14	RX/CX(2)	passive	External Rx-Cx junction for MONO2. Rx (min 5 kΩ) is tied to VDD; Cx to pin 15. Sets one-shot pulse width T ≈ 0.5·Rx·Cx.
15	CX2	passive	External timing capacitor Cx connection for MONO2. Cx is tied between pin 15 (CX2) and pin 14 (Rx·Cx).
16	VDD	power_in	Positive supply voltage input. Recommended operating range 3 V to 18 V; absolute max 20 V referenced to VSS. Rx is tied from this rail to the Rx·Cx pin of each monostable.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOP-16
Category	Logic
Pins	16

Ordering variants

Same part, different packaging or reel option.

CD4098BM96
CD4098BM96G4
CD4098BM96BMG4
CD4098BM96BMT
CD4098BM96BE
CD4098BM96BEE4
CD4098BM96BF
CD4098BM96BF3A
CD4098BM96BPW
CD4098BM96BPWR
CD4098BM96JM38510/17504BEA
CD4098BM96M38510/17504BEA

CAD (KiCad official)

Symbol: CD4098BM96
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOP-16 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`cd4098bm96.step`	217 KB	You want the bare part, or you mark your own boards.
`cd4098bm96-etched.step`	2.9 MB	You want the part with `CD4098BM96` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 708 faces against 267 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (16 pp, sha256 62822a4549935bcb, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF