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CD4098B Dual Monostable

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by Ray

Dual retriggerable/resettable monostable multivibrator in the 4000B CMOS family.

logicmonostableone-shot4000-seriestisoic-16
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CD4098B

Texas Instruments · Monostable Multivibrator · SOIC-16

The CD4098B contains two retriggerable, resettable monostable multivibrators (one-shots) in the 4000B CMOS family. A trigger edge starts an output pulse set by an external RC, retriggerable during the pulse, with a reset input to end it early. Its wide 3 V to 18 V supply suits higher-voltage timing and pulse generation.

Pinout

Pin Name Type Function
1 Cx(1) passive External timing capacitor C_X1 node for MONO1 (other side of C_X1). Connect C_X1 between pin 1 and pin 2.
2 RxCx(1) passive Timing node for MONO1: junction of external timing resistor R_X1 (to V_DD) and external timing capacitor C_X1. R_X minimum 5 kOhm; C_X maximum 100 uF. Pulse width T = K * R_X * C_X (approx 0.5R_XC_X for C_X >= 0.01 uF).
3 RESET(1) input Active-low RESET input for MONO1. Low level provides immediate termination of the output pulse or prevents output pulses when power is turned on. Tie to V_DD if unused.
4 +TR(1) input Leading-edge (positive-going) trigger input for MONO1. Used when Q1 (pin 6) is connected to +TR for retriggerable leading-edge triggering. Tie to V_SS if unused.
5 -TR(1) input Trailing-edge (negative-going) trigger input for MONO1. Used when Q1-bar (pin 7) is connected to -TR for retriggerable trailing-edge triggering. Tie to V_DD if unused.
6 Q1 output Buffered true output of MONO1. Active-high one-shot pulse output. V_OH >= V_DD - 0.05 V typical; I_OH up to 6.8 mA at 15 V.
7 Q1_N output Buffered complementary (inverted) output of MONO1. Active-low one-shot pulse output.
8 VSS power_in Negative supply / ground reference. Voltage referenced to V_SS terminal; supply voltage V_DD to V_SS = -0.5 V to +20 V absolute maximum, recommended 3-18 V.
9 Q2_N output Buffered complementary (inverted) output of MONO2. Active-low one-shot pulse output.
10 Q2 output Buffered true output of MONO2. Active-high one-shot pulse output.
11 -TR(2) input Trailing-edge (negative-going) trigger input for MONO2. Used when Q2-bar (pin 9) is connected to -TR for retriggerable trailing-edge triggering. Tie to V_DD if unused.
12 +TR(2) input Leading-edge (positive-going) trigger input for MONO2. Used when Q2 (pin 10) is connected to +TR for retriggerable leading-edge triggering. Tie to V_SS if unused.
13 RESET(2) input Active-low RESET input for MONO2. Low level provides immediate termination of the output pulse or prevents output pulses when power is turned on. Tie to V_DD if unused.
14 RxCx(2) passive Timing node for MONO2: junction of external timing resistor R_X2 (to V_DD) and external timing capacitor C_X2. R_X minimum 5 kOhm; C_X maximum 100 uF.
15 Cx(2) passive External timing capacitor C_X2 node for MONO2 (other side of C_X2). Connect C_X2 between pin 15 and pin 14.
16 VDD power_in Positive supply. Recommended operating range 3 V to 18 V (absolute max V_DD to V_SS = 20 V). External timing resistors R_X1 and R_X2 also connect to V_DD.

Key specifications

Parameter Value
Type Dual retriggerable monostable (one-shot)
Logic family 4000B (CMOS)
Timing External R and C set pulse width
Features Retriggerable, resettable, both edges
Supply voltage 3 V to 18 V
Operating temperature -55 C to 125 C

Ordering variants

Same part, different packaging or reel option.

  • CD4098BE
  • CD4098BF3A
  • CD4098BM
  • CD4098BM96
  • CD4098BMT
  • CD4098BPW
  • CD4098BPWR

CAD (KiCad official)

  • Symbol: cd4098.kicad_sym
  • Footprint: cd4098.kicad_mod
  • 3D model: SOIC-16 body from KiCad Package_SO/SOIC-16_3.9x9.9mm_P1.27mm.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (17 pp, sha256 7e13a3425e4310ba, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF