CD4060BDTR from XBLW, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	Q11	output	Buffered output of counter stage 12 (divide-by-4096). CMOS output, VDD swing.
2	Q12	output	Buffered output of counter stage 13 (divide-by-8192). CMOS output, VDD swing.
3	Q13	output	Buffered output of counter stage 14 (divide-by-16384). CMOS output, VDD swing.
4	Q9	output	Buffered output of counter stage 10 (divide-by-1024). CMOS output, VDD swing.
5	Q8	output	Buffered output of counter stage 9 (divide-by-512). CMOS output, VDD swing.
6	Q7	output	Buffered output of counter stage 8 (divide-by-256). CMOS output, VDD swing.
7	Q5	output	Buffered output of counter stage 6 (divide-by-64). CMOS output, VDD swing.
8	VSS	power_in	Ground reference (0 V).
9	RS	output	Oscillator RC network connection (reset/feedback node between external RS and CTC of the RC oscillator).
10	RTC	input	Oscillator RC timing input node (RTC / external clock input when oscillator is not used).
11	CTC	passive	Oscillator timing capacitor connection (CTC).
12	RESET	input	Master reset input. A logic HIGH clears all counter stages and disables the oscillator; must be held LOW for normal counting.
13	Q6	output	Buffered output of counter stage 7 (divide-by-128). CMOS output, VDD swing.
14	Q4	output	Buffered output of counter stage 5 (divide-by-32). CMOS output, VDD swing.
15	Q3	output	Buffered output of counter stage 4 (divide-by-16). CMOS output, VDD swing.
16	VDD	power_in	Positive supply voltage. Operating range 3 V to 18 V.

Key specifications

Parameter	Value
Manufacturer	XBLW
Package	SOP-16
Category	Logic
Pins	16

Ordering variants

Same part, different packaging or reel option.

CD4060BDTR
CD4060BDTRD
CD4060BDTRPW
CD4060BDTRPWR
CD4060BDTRN
CD4060BDTRE

CAD (KiCad official)

Symbol: CD4060BDTR
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOP-16 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`cd4060bdtr.step`	217 KB	You want the bare part, or you mark your own boards.
`cd4060bdtr-etched.step`	2.7 MB	You want the part with `CD4060BDTR` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 658 faces against 267 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: XBLW datasheet (15 pp, sha256 fc074a4a0bd1cffe, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF