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CD4022B Octal Counter
Public Unreviewedby Ray
Divide-by-8 (octal) Johnson counter with 8 decoded outputs, 4000B CMOS.
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markdownCD4022B
Texas Instruments · Counter · SOIC-16
The CD4022B is a divide-by-8 (octal) Johnson counter with eight fully decoded, mutually exclusive outputs and a carry-out for cascading. Each clock advances one active output in sequence, making it a simple sequencer or 1-of-8 timing generator. It runs from 3 V to 18 V.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Q1 | output | Decoded output '1'. High for one clock cycle when count = 1; otherwise low. CMOS push-pull, sourcing/sinking a few mA. |
| 2 | Q0 | output | Decoded output '0'. High for one clock cycle when the counter is at zero (also on reset). |
| 3 | Q2 | output | Decoded output '2'. High for one clock cycle when count = 2. |
| 4 | Q5 | output | Decoded output '5'. High for one clock cycle when count = 5. |
| 5 | Q6 | output | Decoded output '6'. High for one clock cycle when count = 6. |
| 6 | NC | unconnected | No internal connection on the CD4022B (this pin is used on CD4017B for a decoded output). |
| 7 | Q3 | output | Decoded output '3'. High for one clock cycle when count = 3. |
| 8 | VSS | power_in | Negative supply / ground reference (0 V). |
| 9 | NC | unconnected | No internal connection on the CD4022B (this pin is a decoded output on CD4017B). |
| 10 | Q7 | output | Decoded output '7'. High for one clock cycle when count = 7. |
| 11 | Q4 | output | Decoded output '4'. High for one clock cycle when count = 4. |
| 12 | CARRY_OUT | output | Carry output. Completes one full cycle every 8 clock inputs; used to ripple-clock the next device in a cascade. |
| 13 | CLOCK_INHIBIT | input | Active-high clock inhibit. When high, counter advancement via the CLOCK line is disabled. Setup time tS = 230/100/70 ns at 5/10/15 V. |
| 14 | CLOCK | input | Schmitt-triggered clock input. Counter advances on the positive-going transition when CLOCK INHIBIT is low. fCL_max = 2.5/5/5.5 MHz at 5/10/15 V. |
| 15 | RESET | input | Active-high asynchronous reset. Clears the counter to zero (Q0 high) while held high. Minimum pulse width 260/110/60 ns at 5/10/15 V. |
| 16 | VDD | power_in | Positive supply, 3-18 V (absolute max VDD-VSS = 20 V). |
Key specifications
| Parameter | Value |
|---|---|
| Type | Divide-by-8 Johnson counter |
| Logic family | 4000B (CMOS) |
| Outputs | 8 decoded (1-of-8) + carry-out |
| Supply voltage | 3 V to 18 V |
| Operating temperature | -55 C to 125 C |
Ordering variants
Same part, different packaging or reel option.
CD4022BECD4022BF3ACD4022BNSRCD4022BPWCD4022BPWR
CAD (KiCad official)
- Symbol:
cd4022.kicad_sym - Footprint:
cd4022.kicad_mod - 3D model: SOIC-16 body from KiCad
Package_SO/SOIC-16_3.9x9.9mm_P1.27mm.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (22 pp, sha256
33e12c4baa664425, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).