CD4021BM96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	P1-8	input	Parallel (JAM) data input for stage 8 (PI-8). When PARALLEL/SERIAL CONTROL is high the level on this pin is asynchronously jammed into the 8th register stage. High-impedance CMOS input; VIH >= 3.5 V at VDD=5 V, 7 V at 10 V, 11 V at 15 V.
2	Q6	output	Buffered non-inverting parallel output of register stage 6. CMOS push-pull output; VOH >= 4.95 V at VDD=5 V, IOH typ. -1 mA. Reflects the state of the 6th stage flip-flop (updated on the rising CLOCK edge in serial mode or asynchronously in parallel mode).
3	Q8	output	Buffered non-inverting parallel output of register stage 8 (last stage, also used as serial-out for cascading). CMOS push-pull output; VOH >= 4.95 V at VDD=5 V, IOH typ. -1 mA.
4	P1-4	input	Parallel (JAM) data input for stage 4 (PI-4). Asynchronously loaded into stage 4 while PARALLEL/SERIAL CONTROL is high. High-impedance CMOS logic input.
5	P1-3	input	Parallel (JAM) data input for stage 3 (PI-3). Asynchronously loaded into stage 3 while PARALLEL/SERIAL CONTROL is high. High-impedance CMOS logic input.
6	P1-2	input	Parallel (JAM) data input for stage 2 (PI-2). Asynchronously loaded into stage 2 while PARALLEL/SERIAL CONTROL is high. High-impedance CMOS logic input.
7	P1-1	input	Parallel (JAM) data input for stage 1 (PI-1). Asynchronously loaded into stage 1 while PARALLEL/SERIAL CONTROL is high. High-impedance CMOS logic input.
8	VSS	power_in	Negative supply / ground reference. Typically tied to 0 V. All input and output voltages are referenced to VSS.
9	PARALLEL/SERIAL CONTROL	input	Mode-select input. When HIGH, the eight parallel P1-1..P1-8 inputs are asynchronously jammed into the register (parallel load). When LOW, data at SERIAL IN is shifted synchronously through the 8 stages on the positive edge of CLOCK. Minimum P/S pulse width (tWH): 160/80/50 ns at VDD=5/10/15 V; minimum removal time (tREM) before the next CLOCK edge: 280/140/100 ns.
10	CLOCK	input	Shift clock input. On the positive-going transition of CLOCK the serial data at SERIAL IN is loaded into stage 1 and each stage is shifted to the next. Max clock frequency (fCL): 3 MHz at VDD=5 V, 6 MHz at 10 V, 8.5 MHz at 15 V. Minimum clock pulse width (tW): 180/80/50 ns; rise/fall time <= 15 us.
11	SERIAL IN	input	Serial data input to stage 1. Sampled synchronously with the positive edge of CLOCK when PARALLEL/SERIAL CONTROL is low. Set-up time (ts) 120/80/60 ns at VDD=5/10/15 V; hold time 0 ns.
12	Q7	output	Buffered non-inverting parallel output of register stage 7. CMOS push-pull output; VOH >= 4.95 V at VDD=5 V.
13	P1-5	input	Parallel (JAM) data input for stage 5 (PI-5). Asynchronously loaded into stage 5 while PARALLEL/SERIAL CONTROL is high. High-impedance CMOS logic input.
14	P1-6	input	Parallel (JAM) data input for stage 6 (PI-6). Asynchronously loaded into stage 6 while PARALLEL/SERIAL CONTROL is high. High-impedance CMOS logic input.
15	P1-7	input	Parallel (JAM) data input for stage 7 (PI-7). Asynchronously loaded into stage 7 while PARALLEL/SERIAL CONTROL is high. High-impedance CMOS logic input.
16	VDD	power_in	Positive supply voltage. Recommended operating range 3 V to 18 V referenced to VSS; absolute maximum -0.5 V to +20 V. Quiescent supply current typ. 0.04 uA (5 uA max) at VDD=5 V.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-16
Category	Logic
Pins	16

Ordering variants

Same part, different packaging or reel option.

CD4021BM96
CD4021BM96E4
CD4021BM96G4
CD4021BM96BME4
CD4021BM96BMG4
CD4021BM96BMT
CD4021BM96BMTE4
CD4021BM96BMTG4
CD4021BM96BE
CD4021BM96BEE4
CD4021BM96BF
CD4021BM96BF3A
CD4021BM96BNSR
CD4021BM96BNSRE4
CD4021BM96BNSRG4
CD4021BM96BPW
CD4021BM96BPWE4
CD4021BM96BPWG4
CD4021BM96BPWR
CD4021BM96BPWRE4
CD4021BM96BPWRG4

CAD (KiCad official)

Symbol: CD4021BM96
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOIC-16 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`cd4021bm96.step`	217 KB	You want the bare part, or you mark your own boards.
`cd4021bm96-etched.step`	2.7 MB	You want the part with `CD4021BM96` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 655 faces against 267 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (28 pp, sha256 92ad93f1b6237a10, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF