CD4017CM from HGSEMI, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	Q5	output	Decoded active-high output 5. High during the sixth clock state; typical CMOS output drive at VDD = 5-15 V.
2	Q1	output	Decoded active-high output 1. High during the second clock state.
3	Q0	output	Decoded active-high output 0. High during the first clock state and following reset.
4	Q2	output	Decoded active-high output 2. High during the third clock state.
5	Q6	output	Decoded active-high output 6. High during the seventh clock state.
6	Q7	output	Decoded active-high output 7. High during the eighth clock state.
7	Q3	output	Decoded active-high output 3. High during the fourth clock state.
8	VSS	power_in	Negative supply / ground return. Tie to 0 V.
9	Q8	output	Decoded active-high output 8. High during the ninth clock state.
10	Q4	output	Decoded active-high output 4. High during the fifth clock state.
11	Q9	output	Decoded active-high output 9. High during the tenth clock state.
12	CARRY_OUT	output	Carry-out. Completes one full cycle every 10 clock input cycles; used to cascade CD4017 stages as a divide-by-10 chain.
13	CLOCK_INHIBIT	input	Clock inhibit / clock-enable. When high, the counter is inhibited and holds its current state; when low, the counter advances on the positive clock edge.
14	CLOCK	input	Clock input. The counter advances one count on each positive-going clock transition while CLOCK_INHIBIT and RESET are low.
15	RESET	input	Asynchronous reset (active high). Forces the counter to state 0 (Q0 high, all other outputs low) independent of the clock.
16	VDD	power_in	Positive supply. Operating range 3 V to 15 V (absolute max 18 V).

Key specifications

Parameter	Value
Manufacturer	HGSEMI
Package	SOP-16
Category	Logic
Pins	16

Ordering variants

Same part, different packaging or reel option.

CD4017BE
CD4017BM
CD4017BPW

CAD (KiCad official)

Symbol: CD4017CM
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOP-16 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`cd4017cm.step`	217 KB	You want the bare part, or you mark your own boards.
`cd4017cm-etched.step`	1.9 MB	You want the part with `CD4017CM` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 503 faces against 267 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: HGSEMI datasheet (16 pp, sha256 141ca40d50613ba8, retrieved 2026-08-17, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF