A CMOS decade counter/divider in DIP-16, the chip behind countless LED chasers and sequencers. It is a Johnson counter that decodes to ten outputs (Q0-Q9): exactly one goes high at a time, stepping to the next on each clock rising edge. A carry-out pulses once every ten counts so devices cascade for counting past ten, a clock-inhibit pin freezes the count, and an asynchronous reset returns it to Q0. It runs 3 to 18 V and needs no decoding logic, so a clock plus this chip drives ten LEDs or ten steps directly.

Pinout

Pin	Name	Type	Function
1	Q5	output	Decoded output 5. Goes high during the 6th clock state (count 5). CMOS push-pull output; typical IOH/IOL ~1 mA at VDD=5 V.
2	Q1	output	Decoded output 1. Goes high during count 1.
3	Q0	output	Decoded output 0. Goes high during count 0 (also the state after RESET).
4	Q2	output	Decoded output 2. Goes high during count 2.
5	Q6	output	Decoded output 6. Goes high during count 6.
6	Q7	output	Decoded output 7. Goes high during count 7.
7	Q3	output	Decoded output 3. Goes high during count 3.
8	VSS	power_in	Negative supply / ground reference (0 V).
9	Q8	output	Decoded output 8. Goes high during count 8.
10	Q4	output	Decoded output 4. Goes high during count 4.
11	Q9	output	Decoded output 9. Goes high during count 9.
12	CARRY_OUT	output	Carry output. Completes one full cycle every 10 clock inputs (high for counts 0-4, low for counts 5-9); useful for cascading counters.
13	CLOCK_INHIBIT	input	Active-high clock inhibit. Counter advances on the positive clock transition only when this signal is low; hold high to freeze the count.
14	CLOCK	input	Clock input with Schmitt-trigger action; permits unlimited input pulse rise/fall times. Counter advances on the positive-going clock edge. Max fCL 5 MHz @ VDD=10 V.
15	RESET	input	Active-high asynchronous reset. Clears the counter to state 0 (Q0 high, Q1-Q9 low) while held high.
16	VDD	power_in	Positive supply. Operating range 3 V to 18 V (absolute max -0.5 V to +20 V referenced to VSS).

Key specifications

Parameter	Value
Type	Decade counter / divider (Johnson)
Outputs	10 decoded (Q0-Q9, 1 high at a time)
Carry out	1 pulse per 10 counts (cascade)
Control	clock, clock-inhibit, async reset
Clocking	advances on rising edge
Supply voltage	3-18 V
Logic family	4000B CMOS
Package	PDIP-16

Ordering variants

Same part, different packaging or reel option.

CD4017BE (PDIP-16)
CD4017BM96 (SOIC-16, tape & reel)

CAD (KiCad official)

Symbol: 4xxx:4017
Footprint: Package_DIP:DIP-16_W7.62mm
3D model: DIP-16 (KiCad packages3D)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (22 pp, sha256 33e12c4baa664425, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF