Two D-type flip-flops in one SOIC-14, the 4000-series CMOS counterpart of the 74HC74. On each rising clock edge Q takes the value on D, and asynchronous active-high SET and RESET inputs override the clock to force the output. Complementary Q and Q outputs are provided. Its wide 3 to 18 V supply and CMOS inputs suit it to simple dividers (wire Q back to D for divide-by-two), toggle latches, debouncers, and slow logic where the 74HC74's tighter voltage range is a limitation.

Pinout

Pin	Name	Type	Function
1	Q1	output	Channel 1 true (Q) output of the D flip-flop. CMOS push-pull; sources approx -0.51 mA and sinks approx 0.51 mA at VDD = 5 V. Follows D1 on the rising edge of CLOCK1.
2	Q1_N	output	Inverted channel 1 output (Q̄). Complement of Q1 with the same CMOS drive characteristics.
3	CLOCK1	input	Channel 1 clock input. Data on D1 is transferred to Q1 on the positive-going edge. Max clock frequency 3.5 MHz (VDD = 5 V) to 12 MHz (VDD = 15 V).
4	RESET1	input	Channel 1 asynchronous reset. A high level forces Q1 = 0 (Q̄ = 1) independent of CLOCK1. Min pulse width 180 ns at VDD = 5 V.
5	D1	input	Channel 1 data input. Sampled on the positive-going edge of CLOCK1 and transferred to Q1. CMOS input, ~1 µA max at VDD = 18 V.
6	SET1	input	Channel 1 asynchronous set. A high level forces Q1 = 1 (Q̄ = 0) independent of CLOCK1. Min pulse width 180 ns at VDD = 5 V.
7	VSS	power_in	Negative supply / ground reference (0 V). All voltages in the datasheet are referenced to VSS.
8	SET2	input	Channel 2 asynchronous set. A high level forces Q2 = 1 (Q̄ = 0) independent of CLOCK2.
9	D2	input	Channel 2 data input. Sampled on the positive-going edge of CLOCK2 and transferred to Q2.
10	RESET2	input	Channel 2 asynchronous reset. A high level forces Q2 = 0 independent of CLOCK2.
11	CLOCK2	input	Channel 2 clock input. Data on D2 is transferred to Q2 on the positive-going edge. Same fCL limits as CLOCK1.
12	Q2_N	output	Inverted channel 2 output (Q̄). Complement of Q2 with the same CMOS drive characteristics.
13	Q2	output	Channel 2 true (Q) output. CMOS push-pull output; follows D2 on the rising edge of CLOCK2.
14	VDD	power_in	Positive supply. Recommended operating range 3 V to 18 V (abs-max 20 V). Quiescent current ~0.02 µA typical at 25 °C.

Key specifications

Parameter	Value
Type	Dual D-type flip-flop
Trigger	positive (rising) clock edge
Async controls	SET + RESET (active-high)
Outputs	Q + Q (complementary)
Logic family	4000B CMOS
Supply voltage	3-18 V
Common uses	dividers, latches, debounce
Package	SOIC-14

Ordering variants

Same part, different packaging or reel option.

CD4013BM (SOIC-14, tube)
CD4013BM96 (SOIC-14, tape & reel)

CAD (KiCad official)

Symbol: 4xxx:4013
Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
3D model: SOIC-14 (KiCad packages3D)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (31 pp, sha256 dea158db743cc96d, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF