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CD4011B Quad NAND Gate

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by Ray

Quad 2-input NAND gate in the 4000B CMOS family, 3 V to 18 V.

logicnand-gatecmos4000-seriestisoic-14
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CD4011B

Texas Instruments · Logic Gate · SOIC-14

The CD4011B contains four independent 2-input NAND gates in the 4000B CMOS family. Its wide 3 V to 18 V supply range makes it a common building block for RC oscillators, set-reset latches, and general logic in higher-voltage designs.

Pinout

Pin Name Type Function
1 1A input Gate 1 input A. High-impedance CMOS logic input to the first 2-input NAND gate; VIL max = 1.5 V at VDD=5 V, VIH min = 3.5 V at VDD=5 V. Protected by on-chip input clamp diodes to VDD and VSS.
2 1B input Gate 1 input B. High-impedance CMOS logic input to the first 2-input NAND gate; input current typ 10 pA (IIN max 0.1 µA at VDD=18 V). Protected by CMOS input protection network.
3 1Y output Gate 1 output (NAND of pins 1 and 2). Buffered CMOS push-pull output; IOL min = 1.0 mA sink and IOH min = -1.0 mA source at VDD=5 V (VO=0.4 V / 4.6 V).
4 2Y output Gate 2 output (NAND of pins 5 and 6). Buffered CMOS push-pull output; symmetrical drive characteristics per JEDEC Standard No. 13B for B-series CMOS.
5 2A input Gate 2 input A. High-impedance CMOS logic input to the second 2-input NAND gate; noise margin 1 V at VDD=5 V, 2 V at VDD=10 V, 2.5 V at VDD=15 V over full package temperature range.
6 2B input Gate 2 input B. High-impedance CMOS logic input to the second 2-input NAND gate; DC input current ±10 mA absolute maximum per input.
7 VSS power_in Negative supply / ground reference. All input and output voltages are referenced to this pin. Tie to 0 V for single-supply operation.
8 3A input Gate 3 input A. High-impedance CMOS logic input to the third 2-input NAND gate; input capacitance CIN typ 5 pF (max 7.5 pF).
9 3B input Gate 3 input B. High-impedance CMOS logic input to the third 2-input NAND gate; input voltage range VSS-0.5 V to VDD+0.5 V absolute maximum.
10 3Y output Gate 3 output (NAND of pins 8 and 9). Buffered CMOS output; VOL max = 0.05 V and VOH min = 4.95 V at VDD=5 V (no load).
11 4Y output Gate 4 output (NAND of pins 12 and 13). Buffered CMOS output; typical propagation delay tPHL/tPLH = 60 ns at VDD=10 V, CL=50 pF, RL=200 kΩ.
12 4A input Gate 4 input A. High-impedance CMOS logic input to the fourth 2-input NAND gate; all inputs protected by on-chip clamp diode network to VDD and VSS.
13 4B input Gate 4 input B. High-impedance CMOS logic input to the fourth 2-input NAND gate; standardized symmetrical output characteristics per B-series CMOS spec.
14 VDD power_in Positive supply. Recommended operating range 3 V to 18 V (VDD-VSS); absolute maximum -0.5 V to +20 V referenced to VSS. Quiescent current IDD typ 0.01 µA (max 1 µA) at VDD=10 V, TA=25 °C.

Key specifications

Parameter Value
Type Quad 2-input NAND gate
Logic family 4000B (CMOS)
Supply voltage 3 V to 18 V
Propagation delay 60 ns typ at 10 V
Quiescent current 0.04 uA typ at 5 V
Operating temperature -55 C to 125 C

Ordering variants

Same part, different packaging or reel option.

  • CD4011BE
  • CD4011BEE4
  • CD4011BN
  • CD4011BF
  • CD4011BF3A
  • CD4011BJ
  • CD4011BM
  • CD4011BM96
  • CD4011BMT
  • CD4011BME4
  • CD4011BM96E4
  • CD4011BD
  • CD4011BNSR
  • CD4011BNS
  • CD4011BPW
  • CD4011BPWR
  • CD4011BPWRG4

CAD (KiCad official)

  • Symbol: cd4011.kicad_sym
  • Footprint: cd4011.kicad_mod
  • 3D model: SOIC-14 body from KiCad Package_SO/SOIC-14_3.9x8.7mm_P1.27mm.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (23 pp, sha256 92d82fa35555e4e4, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF