component
BR24G08F-3GTE2
Public Unreviewedby Ray
ROHM EEPROM, SOP-8-4.4mm. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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README
markdownBR24G08F-3GTE2
ROHM · EEPROM · SOP-8-4.4mm
BR24G08F-3GTE2 from ROHM, in a SOP-8-4.4mm. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A0 | input | Device address input A0. For BR24G08-3 this pin is not used to select the device address (the memory occupies the address space); datasheet states 'Don't use' and it may be left at H, L, or Hi-Z. Typically tied to GND on the PCB. |
| 2 | A1 | input | Device address input A1. Not used for device addressing on BR24G08-3; datasheet states 'Don't use' and it may be left at H, L, or Hi-Z. Typically tied to GND. |
| 3 | A2 | input | Slave address setting input A2. Selects the upper bit of the I2C slave address, allowing two BR24G08-3 devices to share the same bus. Must NOT be left open; drive to VCC or GND. VIH ≥ 0.7·VCC (VCC ≥ 1.7 V) or 0.8·VCC (VCC < 1.7 V); VIL ≤ 0.3·VCC or 0.2·VCC respectively. |
| 4 | GND | power_in | Ground reference (0 V) for all inputs and outputs. |
| 5 | SDA | bidirectional | I2C serial data input/output. Open-drain output requires an external pull-up resistor to VCC. VOL1 ≤ 0.4 V at IOL = 3.0 mA (2.5 V ≤ VCC ≤ 5.5 V); VOL2 ≤ 0.2 V at IOL = 0.7 mA (1.6 V ≤ VCC < 2.5 V). Supports up to fSCL = 400 kHz. |
| 6 | SCL | input | I2C serial clock input, driven by the bus master. Data on SDA is latched on the rising edge of SCL and output on the falling edge. Maximum clock frequency 400 kHz; noise filter integrated on SCL. |
| 7 | WP | input | Write-protect input. When held High, all write operations to the EEPROM array are inhibited (read operations still function). When Low, writes are allowed. Must not be left open. |
| 8 | VCC | power_in | Positive supply input. Operating range 1.6 V to 5.5 V; absolute maximum 6.5 V. Recommend a 0.1 µF bypass capacitor placed close to the pin between VCC and GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | ROHM |
| Package | SOP-8-4.4mm |
| Category | Memory |
| Pins | 8 |
Ordering variants
BR24G08F-3GTE2BR24G08F-3GTE2-3NE2BR24G08F-3GTE2-3GE2BR24G08F-3GTE2-3GTTRBR24G08F-3GTE2-3TTR
CAD (KiCad official)
- Symbol:
BR24G08F-3GTE2 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8-4.4mm (KiCad packages3D, STEP)
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
br24g08f-3gte2.step |
122 KB | You want the bare part, or you mark your own boards. |
br24g08f-3gte2-etched.step |
3.0 MB | You want the part with BR24G08F-3GTE2 already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 717 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: ROHM datasheet (41 pp, sha256
b353d58ad7ea1970, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).