BQ76952PFBR from Texas Instruments, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VC15	input	Sense voltage input for the 15th cell from the bottom of the stack; balance current input for the 15th cell and return balance current for the 16th cell. Analog input (IA), up to VSS+85V.
2	VC14	input	Sense voltage input for the 14th cell; balance current input for the 14th cell and return balance current for the 15th cell. Analog input (IA), up to VSS+85V.
3	VC13	input	Sense voltage input for the 13th cell; balance current input for the 13th cell and return balance current for the 14th cell. Analog input (IA), up to VSS+85V.
4	VC12	input	Sense voltage input for the 12th cell; balance current input for the 12th cell and return balance current for the 13th cell.
5	VC11	input	Sense voltage input for the 11th cell; balance current input for the 11th cell and return balance current for the 12th cell.
6	VC10	input	Sense voltage input for the 10th cell; balance current input for the 10th cell and return balance current for the 11th cell.
7	VC9	input	Sense voltage input for the 9th cell; balance current input for the 9th cell and return balance current for the 10th cell.
8	VC8	input	Sense voltage input for the 8th cell; balance current input for the 8th cell and return balance current for the 9th cell.
9	VC7	input	Sense voltage input for the 7th cell; balance current input for the 7th cell and return balance current for the 8th cell.
10	VC6	input	Sense voltage input for the 6th cell; balance current input for the 6th cell and return balance current for the 7th cell.
11	VC5	input	Sense voltage input for the 5th cell; balance current input for the 5th cell and return balance current for the 6th cell.
12	VC4	input	Sense voltage input for the 4th cell; balance current input for the 4th cell and return balance current for the 5th cell.
13	VC3	input	Sense voltage input for the 3rd cell; balance current input for the 3rd cell and return balance current for the 4th cell.
14	VC2	input	Sense voltage input for the 2nd cell; balance current input for the 2nd cell and return balance current for the 3rd cell.
15	VC1	input	Sense voltage input for the 1st (bottom) cell; balance current input for the 1st cell and return balance current for the 2nd cell.
16	VC0	input	Sense voltage input for the negative terminal of the bottom cell, and return balance current for the 1st cell.
17	VSS	power_in	Device ground reference.
18	SRP	input	Analog input to the internal coulomb-counter peripheral. SRP is the top (positive) of the current-sense resistor; a charging current generates a positive voltage from SRP to SRN. Absolute range VSS-0.3 to VREG18+0.3 V.
19	NC	unconnected	Not connected to silicon.
20	SRN	input	Analog input to the internal coulomb-counter peripheral. SRN is the bottom (negative) side of the current-sense resistor. Absolute range VSS-0.3 to VREG18+0.3 V.
21	TS1	bidirectional	Thermistor input or general-purpose ADC input (OD, I/OA). Configurable via device data memory.
22	TS2	bidirectional	Thermistor input; also serves as wakeup from SHUTDOWN. Alternately general-purpose ADC input (OD, I/OA).
23	TS3	bidirectional	Thermistor input, or general-purpose ADC input (OD, I/OA).
24	REG18	power_out	Internal 1.8-V LDO output. For internal device use only; bypass capacitor required.
25	ALERT	bidirectional	Multifunction pin: ALERT interrupt output, HDQ I/O, thermistor input, general-purpose ADC input, or general-purpose digital output. I/OD, I/OA.
26	SCL	bidirectional	Multifunction serial-clock pin: I2C SCL or SPI SCLK, selected by the device variant/configuration. I/OD.
27	SDA	bidirectional	Multifunction serial-data pin: I2C SDA or SPI MISO, selected by device configuration. I/OD.
28	HDQ	bidirectional	Multifunction pin: HDQ single-wire I/O, SPI MOSI, thermistor input, general-purpose ADC input, or general-purpose digital output. I/OD, I/OA.
29	CFETOFF	bidirectional	Multifunction pin: CFETOFF charge-FET-off control input, SPI CS, thermistor input, general-purpose ADC input, or general-purpose digital output. I/OD, I/OA.
30	DFETOFF	bidirectional	Multifunction pin: DFETOFF discharge-FET-off control, BOTHOFF, thermistor input, general-purpose ADC input, or general-purpose digital output. I/OD, I/OA.
31	DCHG	bidirectional	Multifunction pin: DCHG deep-charge status output, thermistor input, general-purpose ADC input, or general-purpose digital output. OD, I/OA.
32	DDSG	bidirectional	Multifunction pin: DDSG deep-discharge status output, thermistor input, general-purpose ADC input, or general-purpose digital output. OD, I/OA.
33	RST_SHUT	input	Digital input pin for reset or shutdown control (ID). Absolute range VSS-0.3 to VSS+6 V.
34	REG2	power_out	Second programmable LDO output. Selectable output of 1.8, 2.5, 3.0, 3.3, or 5.0 V for powering external circuitry.
35	REG1	power_out	First programmable LDO output. Selectable output of 1.8, 2.5, 3.0, 3.3, or 5.0 V for powering external circuitry.
36	REGIN	power_in	Input pin for the REG1 and REG2 LDOs; typically fed from the external preregulator driven by BREG.
37	BREG	output	Base control signal for the external preregulator transistor used to derive REGIN from the pack voltage.
38	FUSE	bidirectional	Chemical-fuse sense and drive pin. Drives external fuse for secondary protection; absolute range up to VSS+20 V or VBAT+0.3.
39	PDSG	output	Predischarge PFET gate-drive output. Controls an external predischarge PFET for soft turn-on of the discharge path.
40	PCHG	output	Precharge PFET gate-drive output. Controls an external precharge PFET for soft turn-on of the charge path.
41	LD	bidirectional	Load-detect pin; connects to the PACK+ side through a bias resistor to detect load or charger insertion. Absolute range VSS-0.3 to VSS+85 V.
42	PACK	input	Pack sense input pin; connects to the PACK+ terminal for pack voltage measurement. Absolute range up to VSS+85 V.
43	DSG	output	NMOS discharge-FET gate-drive output; driven by the internal charge pump for high-side discharge FET control.
44	NC	unconnected	Not connected to silicon.
45	CHG	output	NMOS charge-FET gate-drive output; driven by the internal charge pump for high-side charge FET control.
46	CP1	bidirectional	Charge-pump flying capacitor pin used to build the boosted supply that drives the high-side NFET gates on CHG and DSG.
47	BAT	power_in	Primary power-supply input. Ties to the top of the cell stack; absolute range VSS-0.3 to VSS+85 V.
48	VC16	input	Sense voltage input for the 16th (top) cell; balance current input for the 16th cell and top-of-stack measurement point.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TQFP-48(7x7)
Category	PMIC
Pins	48

Ordering variants

BQ76952PFBR
BQ76952PFBRPFBT

CAD (KiCad official)

Symbol: BQ76952PFBR
Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
3D model: TQFP-48(7x7) (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`bq76952pfbr.step`	617 KB	You want the bare part, or you mark your own boards.
`bq76952pfbr-etched.step`	4.5 MB	You want the part with `BQ76952PFBR` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 1133 faces against 747 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (87 pp, sha256 a9d512dfdac12910, retrieved 2026-08-17, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF