BD41044FJ-CE2 from ROHM, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	TXD	input	Transmission data input from the host microcontroller. Internal pull-up resistor to VCC. LOW drives the CAN bus dominant; HIGH allows the bus recessive. Logic thresholds: VIH >= 0.7VCC, VIL <= 0.3VCC. Protected by TXD dominant time-out (0.8 - 10 ms) in Normal mode.
2	GND	power_in	Ground reference (0 V) for the device.
3	VCC	power_in	Main supply voltage input. Recommended operating range 4.75 V to 5.25 V (typ 5.0 V). Absolute maximum -0.3 V to +7.0 V. Typical operating current: 10 uA (Standby), 5 mA (Normal Recessive), 45 mA (Normal Dominant, 60 ohm load).
4	RXD	output	Receive data output to the host microcontroller. Push-pull CMOS driver: IOH = -1 to -8 mA at VCC-0.4 V, IOL = 1 to 12 mA at 0.4 V. In Normal mode: HIGH = bus recessive, LOW = bus dominant. In Standby mode: HIGH when no wake-up detected, LOW when wake-up request detected. A diode to VCC prevents reverse current in Power-OFF mode.
5	SPLIT	output	Common-mode stabilization output for the CAN bus split-termination network. Outputs VCC/2 in Normal mode (0.45VCC to 0.55VCC at RLOAD=1 MOhm); Hi-Z in Standby and Power-OFF modes. Recommended external capacitor 1.0 - 100 nF (typ 4.7 nF). Absolute maximum -27 V to +40 V.
6	CANL	bidirectional	LOW-level CAN bus line. Differential transceiver I/O driven low during dominant state (typ 1.5 V, VDOM_DIFF 1.5 - 3.0 V into 60 ohm) and biased to VCC/2 during recessive. Absolute maximum -27 V to +40 V; common-mode range -12 V to +12 V; input impedance ~15 kOhm.
7	CANH	bidirectional	HIGH-level CAN bus line. Differential transceiver I/O driven high during dominant state (typ 3.5 V) and biased to VCC/2 during recessive. Absolute maximum -27 V to +40 V; common-mode range -12 V to +12 V; input impedance ~15 kOhm.
8	STB	input	Mode control input with internal pull-up resistor. HIGH selects Standby mode (low-power, wake-up detection only); LOW selects Normal mode (full CAN transceiver operation). Logic thresholds: VIH >= 0.7VCC, VIL <= 0.3VCC. Absolute maximum -0.3 V to +7.0 V.

Key specifications

Parameter	Value
Manufacturer	ROHM
Package	SOIC-8
Category	Interface
Pins	8

Ordering variants

BD41044FJ-CE2

CAD (KiCad official)

Symbol: BD41044FJ-CE2
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`bd41044fj-ce2.step`	122 KB	You want the bare part, or you mark your own boards.
`bd41044fj-ce2-etched.step`	2.2 MB	You want the part with `BD41044FJ-CE2` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 570 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: ROHM datasheet (25 pp, sha256 9e11f04fab71ed08, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF