Single two-input AND gate from TI's AUP ultra-low-power family, in a five-pin SC70. It draws almost nothing static (under 1 uA) and runs from 0.8 to 3.6 V, so it fits battery and always-on logic where a full quad gate would waste space and power. Balanced drive and low dynamic power make it good for glue logic, enable gating, and combining two signals on a compact board. One gate, one job.

Pinout

Pin	Name	Type	Function
1	A	input	Logic input A. Schmitt-trigger CMOS input (Vhys = 250 mV typ at 3.3V). 3.6V-tolerant regardless of VCC.
2	B	input	Logic input B. Schmitt-trigger CMOS input (Vhys = 250 mV typ at 3.3V). 3.6V-tolerant regardless of VCC.
3	GND	power_in	Ground reference (0 V). Connect to system ground with a low-inductance path.
4	Y	output	Logic output Y = A · B (positive-AND). Push-pull CMOS output; tpd = 4.3 ns max at 3.3V.
5	VCC	power_in	Positive supply, 0.8 V to 3.6 V. Bypass locally with a 0.1 µF ceramic capacitor to GND.

Key specifications

Parameter	Value
Type	Single 2-input AND gate
Family	AUP (ultra-low-power)
Supply	0.8-3.6 V
Static current	< 1 uA
Inputs	A, B
Output	Y
Package	SC70-5

Ordering variants

SN74AUP1G08DCKR (SC70-5)
SN74AUP1G08DBVR (SOT-23-5)

CAD (KiCad official)

Symbol: 74xGxx:74AUP1G08 (KiCad official)
Footprint: Package_TO_SOT_SMD:SOT-353_SC-70-5
3D model: SC70-5 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (54 pp, sha256 bf6005a9e1d88684, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF