component
AT24C512CDRG
Public Unreviewedby Ray
HANSCHIP semiconductor EEPROM, SOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Symbol & Footprint
Schematic Symbol
Open full view ↗PCB Footprint
Open full view ↗Datasheet
Open in new tab ↗Contents
README
markdownAT24C512CDRG
HANSCHIP semiconductor · EEPROM · SOP-8
AT24C512CDRG from HANSCHIP semiconductor, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | E0 | input | Device address input bit 0. Hard-wired to VCC or GND to set the 3-bit hardware slave address, allowing up to eight devices on a single I2C bus. Internally pulled down to GND if left floating. |
| 2 | E1 | input | Device address input bit 1. Hard-wired to VCC or GND to set the 3-bit hardware slave address. Internally pulled down to GND if left floating. |
| 3 | E2 | input | Device address input bit 2. Hard-wired to VCC or GND to set the 3-bit hardware slave address. Internally pulled down to GND if left floating. |
| 4 | GND | power_in | Ground reference for the power supply. Must be connected to the system ground. |
| 5 | SDA | bidirectional | Serial Data. Open-drain bidirectional I/O used to serially transfer data to and from the device. Requires an external pull-up resistor to VCC. |
| 6 | SCL | input | Serial Clock. Input clock provided by the I2C master. Command and input data on SDA are latched on the rising edge of SCL; output data on SDA is clocked out on the falling edge of SCL. |
| 7 | WP | input | Write Protect. When tied to VCC, the entire memory array becomes write-protected (read-only); when tied to GND or left floating, write operations are enabled. When driven high, device and word address bytes are ACKed but data bytes are not. |
| 8 | VCC | power_in | Device power supply, 1.7V to 5.5V. Operations at invalid VCC voltages may produce spurious results. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | HANSCHIP semiconductor |
| Package | SOP-8 |
| Category | Memory |
| Pins | 8 |
Ordering variants
AT24C512CDRGAT24C512CDRG4AT24C512CDRGCPGAT24C512CDRGCDGKRGAT24C512CDRGCPWRGAT24C512CDRGCDQRG
CAD (KiCad official)
- Symbol:
AT24C512CDRG - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
at24c512cdrg.step |
122 KB | You want the bare part, or you mark your own boards. |
at24c512cdrg-etched.step |
2.3 MB | You want the part with AT24C512CDRG already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 577 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: HANSCHIP semiconductor datasheet (26 pp, sha256
377ea6b5ad441c21, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).