APL5934DKAI-TRG from Anpec Elec, in a SOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	POK	output	Power-OK signal output. Open-drain output that indicates the status of VOUT by sensing the FB voltage; pulled low when VOUT is outside the Power-OK window (rising POK threshold ~92% of nominal VFB, POK pull-low voltage ~0.25V at 5mA sink). Requires an external pull-up resistor.
2	EN	input	Active-high enable control pin. Holding EN below the enable threshold (~0.8V typical) shuts down the output; re-enabling triggers a new soft-start cycle. An internal ~3µA pull-low current pulls EN low when left open (initial-off for the /D variant), disabling the regulator by default.
3	VIN	power_in	Main power supply input (1.2V ~ 5.5V) used for voltage conversion to VOUT. A ≥10µF decoupling capacitor is recommended close to this pin to filter noise and improve transient response. The voltage on VIN is monitored by the Power-On-Reset circuit (rising VIN POR threshold ~0.9V).
4	VCNTL	power_in	Bias voltage input for the internal control circuitry (3.0V ~ 5.5V, +5V recommended). A 0.1µF decoupling capacitor is typically connected near this pin. VCNTL is also monitored by the Power-On-Reset circuit (rising VCNTL POR threshold ~2.7V).
5	NC	unconnected	No Connection. Leave this pin floating or tie to a convenient net; it has no internal function on the APL5934B/D SOP-8P package.
6	VOUT	power_out	Regulated output pin (0.8V to VIN−VDROP, up to 3A continuous / 4A peak). Requires a minimum 10µF output capacitor (MLCC applicable) for stability and transient response; total COUT scales with load per the datasheet (8-1100µF at 3A). During shutdown an internal ~85Ω pull-down MOSFET quickly discharges VOUT.
7	FB	input	Voltage feedback pin. Connect to the tap of an external resistor divider from VOUT to set the output voltage against the 0.8V internal reference (VOUT = 0.8V × (1 + R1/R2)). FB input current is ±100nA max.
8	GND	power_in	Ground reference pin for all internal circuitry. All voltage levels are measured with respect to this pin.
EP	GND	power_in	Exposed thermal pad on the underside of the SOP-8P package. Connect to the system ground plane with a large copper area for heat dissipation into the ambient air.

Key specifications

Parameter	Value
Manufacturer	Anpec Elec
Package	SOP-8-EP
Category	PMIC
Pins	9

Ordering variants

APL5934DKAI-TRG
APL5934DKAI-TRGAPL5934KA
APL5934DKAI-TRGAPL5934CKA
APL5934DKAI-TRGAPL5934BQB
APL5934DKAI-TRGAPL5934DQB
APL5934DKAI-TRGAPL5934QB
APL5934DKAI-TRGAPL5934CQB
APL5934DKAI-TRGAPL5934EQB

CAD (KiCad official)

Symbol: APL5934DKAI-TRG
Footprint: Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.62x3.51mm
3D model: SOP-8-EP (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`apl5934dkai-trg.step`	194 KB	You want the bare part, or you mark your own boards.
`apl5934dkai-trg-etched.step`	2.2 MB	You want the part with `APL5934DKAI-TRG` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 573 faces against 63 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Anpec Elec datasheet (24 pp, sha256 c5a85a00361edb6c, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF