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Contents

README

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ACS724LLCTR-20AB-T

Allegro MicroSystems LLC · Current Sensors · SOIC-8

ACS724LLCTR-20AB-T from Allegro MicroSystems LLC, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IP+ passive Primary current sense input (positive). Tied internally to pin 2 to form the fused primary conductor (~1.2 mΩ) through which the sensed current flows. Current flowing from pins 1,2 to pins 3,4 produces a positive VIOUT slope.
2 IP+ passive Primary current sense input (positive), internally connected to pin 1. Both pins 1 and 2 must be tied together on the PCB to carry the sensed current.
3 IP- passive Primary current sense return (negative). Tied internally to pin 4 to form the fused primary conductor. Sensed current exits through pins 3 and 4.
4 IP- passive Primary current sense return (negative), internally connected to pin 3. Both pins 3 and 4 must be tied together on the PCB. The IP+/IP- terminals are galvanically isolated (2400 VRMS) from the signal-side pins.
5 GND power_in Signal ground terminal. Reference for VCC, VIOUT, and FILTER on the low-voltage side of the isolation barrier.
6 FILTER passive External capacitor pin (CF) that, combined with the ~1.8 kΩ internal filter resistor RF(int), sets the output bandwidth (default 120 kHz small-signal BW with CF = 1 nF). Reduces noise at lower bandwidths.
7 VIOUT output Analog output signal, ratiometric to VCC. Zero-current output ≈ VCC/2; sensitivity 100 mV/A for the ±20 A -20AB variant. Output impedance drives ≥4.7 kΩ load; saturates near VCC-0.3 V (high) / 0.3 V (low).
8 VCC power_in Device power supply terminal. 5 V single supply nominal (4.5 to 5.5 V operating range, 6 V absolute max). Typical supply current ICC = 10 mA. Bypass with 0.1 µF ceramic (CBYPASS) to GND.

Key specifications

Parameter Value
Manufacturer Allegro MicroSystems LLC
Package SOIC-8
Category Sensor
Pins 8

Ordering variants

  • ACS724LLCTR-20AB-TACS724LLCTR-05AB-T
  • ACS724LLCTR-20AB-TACS724LLCTR-10AU-T
  • ACS724LLCTR-20AB-TACS724LLCTR-10AB-T
  • ACS724LLCTR-20AB-TACS724LLCTR-20AU-T
  • ACS724LLCTR-20AB-T
  • ACS724LLCTR-20AB-TACS724LLCTR-30AU-T
  • ACS724LLCTR-20AB-TACS724LLCTR-30AB-T
  • ACS724LLCTR-20AB-TACS724LLCTR-50AB-T

CAD (KiCad official)

  • Symbol: ACS724LLCTR-20AB-T
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
acs724llctr-20ab-t.step 122 KB You want the bare part, or you mark your own boards.
acs724llctr-20ab-t-etched.step 2.8 MB You want the part with ACS724LLCTR-20AB-T already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 709 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Allegro MicroSystems LLC datasheet (25 pp, sha256 1d287313108ead3b, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF