ACS724LLCTR-10AU-T from Allegro MicroSystems LLC, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	IP+	passive	Terminal for current being sensed (positive side). Pins 1 and 2 are fused internally as one side of the primary copper conduction path (~1.2 mΩ). Galvanically isolated from the signal leads (pins 5-8).
2	IP+	passive	Terminal for current being sensed (positive side). Internally fused with pin 1 as one side of the primary copper conduction path. Must be tied to pin 1 on the PCB to carry the full primary current.
3	IP-	passive	Terminal for current being sensed (return/negative side). Pins 3 and 4 are fused internally as the return side of the primary copper conduction path. Galvanically isolated from the signal leads.
4	IP-	passive	Terminal for current being sensed (return/negative side). Internally fused with pin 3; must be tied to pin 3 on the PCB to carry the full primary current.
5	GND	power_in	Signal ground terminal. Reference for VCC, VIOUT, and the FILTER capacitor.
6	FILTER	passive	External bandwidth-setting capacitor terminal. A capacitor from FILTER to GND forms an RC low-pass with the internal 1.8 kΩ RF(int); a 1 nF cap gives the nominal 120 kHz bandwidth. Larger CF reduces bandwidth and lowers noise.
7	VIOUT	output	Analog output signal proportional to the sensed primary current IP. Ratiometric to VCC with a quiescent output near VCC/2 and 200 mV/A sensitivity (typ) for the -10AU variant. Load: RL ≥ 4.7 kΩ to GND, CL ≤ 10 nF.
8	VCC	power_in	Device power supply terminal. 4.5 V to 5.5 V single supply, ICC typ 10 mA (max 14 mA). Bypass with 0.1 µF CBYPASS to GND close to the pin.

Key specifications

Parameter	Value
Manufacturer	Allegro MicroSystems LLC
Package	SOIC-8
Category	Sensor
Pins	8

Ordering variants

ACS724LLCTR-10AU-T
ACS724LLCTR-10AU-TLLCTR-2P5AB-T
ACS724LLCTR-10AU-TLLCTR-05AB-T
ACS724LLCTR-10AU-TLLCTR-10AB-T
ACS724LLCTR-10AU-TLLCTR-20AU-T
ACS724LLCTR-10AU-TLLCTR-20AB-T
ACS724LLCTR-10AU-TLLCTR-30AU-T
ACS724LLCTR-10AU-TLLCTR-30AB-T
ACS724LLCTR-10AU-TLLCTR-40AU-T
ACS724LLCTR-10AU-TLLCTR-50AB-T

CAD (KiCad official)

Symbol: ACS724LLCTR-10AU-T
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`acs724llctr-10au-t.step`	122 KB	You want the bare part, or you mark your own boards.
`acs724llctr-10au-t-etched.step`	2.7 MB	You want the part with `ACS724LLCTR-10AU-T` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 681 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Allegro MicroSystems LLC datasheet (25 pp, sha256 1b172b64e8e1a4c5, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF