74LVC244APW from Nexperia, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	1OE	input	Output enable input for bank 1 (1Y0-1Y3), active LOW. HIGH forces bank 1 outputs into high-impedance OFF state.
2	1A0	input	Bank 1 data input 0. Schmitt-trigger CMOS input, 5.5 V tolerant; drives buffer output 1Y0 when 1OE is LOW.
3	2Y0	tri_state	Bank 2 data output 0. 3-state CMOS output; drives 2A0 input state when 2OE is LOW, high-impedance when 2OE is HIGH.
4	1A1	input	Bank 1 data input 1. Schmitt-trigger CMOS input, 5.5 V tolerant; drives buffer output 1Y1 when 1OE is LOW.
5	2Y1	tri_state	Bank 2 data output 1. 3-state CMOS output driven by 2A1 when 2OE is LOW.
6	1A2	input	Bank 1 data input 2. Schmitt-trigger CMOS input, 5.5 V tolerant; drives buffer output 1Y2 when 1OE is LOW.
7	2Y2	tri_state	Bank 2 data output 2. 3-state CMOS output driven by 2A2 when 2OE is LOW.
8	1A3	input	Bank 1 data input 3. Schmitt-trigger CMOS input, 5.5 V tolerant; drives buffer output 1Y3 when 1OE is LOW.
9	2Y3	tri_state	Bank 2 data output 3. 3-state CMOS output driven by 2A3 when 2OE is LOW.
10	GND	power_in	Ground reference (0 V).
11	2A3	input	Bank 2 data input 3. Schmitt-trigger CMOS input, 5.5 V tolerant; drives buffer output 2Y3 when 2OE is LOW.
12	1Y3	tri_state	Bank 1 data output 3. 3-state CMOS output driven by 1A3 when 1OE is LOW.
13	2A2	input	Bank 2 data input 2. Schmitt-trigger CMOS input, 5.5 V tolerant; drives buffer output 2Y2 when 2OE is LOW.
14	1Y2	tri_state	Bank 1 data output 2. 3-state CMOS output driven by 1A2 when 1OE is LOW.
15	2A1	input	Bank 2 data input 1. Schmitt-trigger CMOS input, 5.5 V tolerant; drives buffer output 2Y1 when 2OE is LOW.
16	1Y1	tri_state	Bank 1 data output 1. 3-state CMOS output driven by 1A1 when 1OE is LOW.
17	2A0	input	Bank 2 data input 0. Schmitt-trigger CMOS input, 5.5 V tolerant; drives buffer output 2Y0 when 2OE is LOW.
18	1Y0	tri_state	Bank 1 data output 0. 3-state CMOS output driven by 1A0 when 1OE is LOW.
19	2OE	input	Output enable input for bank 2 (2Y0-2Y3), active LOW. HIGH forces bank 2 outputs into high-impedance OFF state.
20	VCC	power_in	Supply voltage. Recommended operating range 1.65 V to 3.6 V (functional down to 1.2 V); absolute max 6.5 V.

Key specifications

Parameter	Value
Manufacturer	Nexperia
Package	TSSOP-20
Category	Logic
Pins	20

Ordering variants

74LVC244APW
74LVC244APWH
74LVC244APWAD
74LVC244APWABQ
74LVC244APWABZ

CAD (KiCad official)

Symbol: 74LVC244APW
Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
3D model: TSSOP-20 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`74lvc244apw.step`	267 KB	You want the bare part, or you mark your own boards.
`74lvc244apw-etched.step`	2.3 MB	You want the part with `74LVC244APW` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 607 faces against 327 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Nexperia datasheet (16 pp, sha256 4195257c91082e34, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF