component
74LVC14AD
Public Unreviewedby Ray
Nexperia Inverters, SOIC-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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README
markdown74LVC14AD
Nexperia · Inverters · SOIC-14
74LVC14AD from Nexperia, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Schmitt-trigger data input for inverter 1. 5 V tolerant (VI up to 5.5 V) with typical hysteresis VH ~0.3 V to 1.2 V depending on VCC. |
| 2 | 1Y | output | Inverted CMOS push-pull data output for inverter 1. Drives up to ±24 mA at VCC = 3.0 V. |
| 3 | 2A | input | Schmitt-trigger data input for inverter 2. 5 V tolerant (VI up to 5.5 V). |
| 4 | 2Y | output | Inverted CMOS push-pull data output for inverter 2. Drives up to ±24 mA at VCC = 3.0 V. |
| 5 | 3A | input | Schmitt-trigger data input for inverter 3. 5 V tolerant (VI up to 5.5 V). |
| 6 | 3Y | output | Inverted CMOS push-pull data output for inverter 3. |
| 7 | GND | power_in | Ground reference (0 V). |
| 8 | 4Y | output | Inverted CMOS push-pull data output for inverter 4. |
| 9 | 4A | input | Schmitt-trigger data input for inverter 4. 5 V tolerant (VI up to 5.5 V). |
| 10 | 5Y | output | Inverted CMOS push-pull data output for inverter 5. |
| 11 | 5A | input | Schmitt-trigger data input for inverter 5. 5 V tolerant (VI up to 5.5 V). |
| 12 | 6Y | output | Inverted CMOS push-pull data output for inverter 6. |
| 13 | 6A | input | Schmitt-trigger data input for inverter 6. 5 V tolerant (VI up to 5.5 V). |
| 14 | VCC | power_in | Supply voltage. Recommended 1.65 V to 3.6 V (functional down to 1.2 V); absolute max 6.5 V. Decouple with 100 nF close to the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
Ordering variants
74LVC14AD74LVC14AD74LVC14APW74LVC14AD74LVC14ABQ74LVC14AD74LVC14ABZ
CAD (KiCad official)
- Symbol:
74LVC14AD - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
74lvc14ad.step |
195 KB | You want the bare part, or you mark your own boards. |
74lvc14ad-etched.step |
1.6 MB | You want the part with 74LVC14AD already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 444 faces against 237 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (16 pp, sha256
b324cd3540deacdc, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).