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74LV04ATPWJ

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Nexperia Inverters, TSSOP-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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74LV04ATPWJ

Nexperia · Inverters · TSSOP-14

74LV04ATPWJ from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Data input to inverter gate 1. TTL-compatible Schmitt-trigger input; VIH >= 2 V, VIL <= 0.8 V over VCC = 4.5 V to 5.5 V.
2 1Y output Data output of inverter gate 1 (logical inverse of 1A). Push-pull CMOS output; VOH >= 3.8 V at IO = -12 mA, VOL <= 0.55 V at IO = 12 mA (VCC = 4.5 V).
3 2A input Data input to inverter gate 2. TTL-compatible Schmitt-trigger input; VIH >= 2 V, VIL <= 0.8 V over VCC = 4.5 V to 5.5 V.
4 2Y output Data output of inverter gate 2 (logical inverse of 2A). Push-pull CMOS output; VOH >= 3.8 V at IO = -12 mA, VOL <= 0.55 V at IO = 12 mA (VCC = 4.5 V).
5 3A input Data input to inverter gate 3. TTL-compatible Schmitt-trigger input; VIH >= 2 V, VIL <= 0.8 V over VCC = 4.5 V to 5.5 V.
6 3Y output Data output of inverter gate 3 (logical inverse of 3A). Push-pull CMOS output; VOH >= 3.8 V at IO = -12 mA, VOL <= 0.55 V at IO = 12 mA (VCC = 4.5 V).
7 GND power_in Ground reference (0 V). All voltages in the datasheet are referenced to this pin.
8 4Y output Data output of inverter gate 4 (logical inverse of 4A). Push-pull CMOS output; VOH >= 3.8 V at IO = -12 mA, VOL <= 0.55 V at IO = 12 mA (VCC = 4.5 V).
9 4A input Data input to inverter gate 4. TTL-compatible Schmitt-trigger input; VIH >= 2 V, VIL <= 0.8 V over VCC = 4.5 V to 5.5 V.
10 5Y output Data output of inverter gate 5 (logical inverse of 5A). Push-pull CMOS output; VOH >= 3.8 V at IO = -12 mA, VOL <= 0.55 V at IO = 12 mA (VCC = 4.5 V).
11 5A input Data input to inverter gate 5. TTL-compatible Schmitt-trigger input; VIH >= 2 V, VIL <= 0.8 V over VCC = 4.5 V to 5.5 V.
12 6Y output Data output of inverter gate 6 (logical inverse of 6A). Push-pull CMOS output; VOH >= 3.8 V at IO = -12 mA, VOL <= 0.55 V at IO = 12 mA (VCC = 4.5 V).
13 6A input Data input to inverter gate 6. TTL-compatible Schmitt-trigger input; VIH >= 2 V, VIL <= 0.8 V over VCC = 4.5 V to 5.5 V.
14 VCC power_in Positive supply voltage. Recommended operating range 4.5 V to 5.5 V (absolute max +7.0 V). Bypass with a local decoupling capacitor to GND.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-14
Category Logic
Pins 14

Ordering variants

Same part, different packaging or reel option.

  • 74LV04ATPWJ

CAD (KiCad official)

  • Symbol: 74LV04ATPWJ
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: 74lv04atpwj-etched.step / 74lv04atpwj-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74lv04atpwj.step / 74lv04atpwj.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (10 pp, sha256 f106d4c0a76bf5eb, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF