74HCT573D from Nexperia, in a SOIC-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	/OE	input	3-state output enable, active LOW. LOW enables the Qn outputs; HIGH places all Q0..Q7 into a high-impedance OFF-state without affecting the internal latch contents.
2	D0	input	Data input bit 0 to latch 1. TTL-level input; sampled on the HIGH-to-LOW LE edge. Input clamp diodes allow interfacing above VCC via a current-limiting resistor.
3	D1	input	Data input bit 1 to latch 2. TTL-level input; sampled on the HIGH-to-LOW LE edge.
4	D2	input	Data input bit 2 to latch 3. TTL-level input; sampled on the HIGH-to-LOW LE edge.
5	D3	input	Data input bit 3 to latch 4. TTL-level input; sampled on the HIGH-to-LOW LE edge.
6	D4	input	Data input bit 4 to latch 5. TTL-level input; sampled on the HIGH-to-LOW LE edge.
7	D5	input	Data input bit 5 to latch 6. TTL-level input; sampled on the HIGH-to-LOW LE edge.
8	D6	input	Data input bit 6 to latch 7. TTL-level input; sampled on the HIGH-to-LOW LE edge.
9	D7	input	Data input bit 7 to latch 8. TTL-level input; sampled on the HIGH-to-LOW LE edge.
10	GND	power_in	Ground reference (0 V) for the device.
11	LE	input	Latch enable input, active HIGH. When LE is HIGH the latches are transparent (Qn follows Dn); the data present one set-up time before the HIGH-to-LOW LE transition is stored when LE goes LOW.
12	Q7	tri_state	3-state latch output bit 7. Drives the stored latch state when /OE=LOW; high-impedance when /OE=HIGH. Rated
13	Q6	tri_state	3-state latch output bit 6. Drives the stored latch state when /OE=LOW; high-impedance when /OE=HIGH.
14	Q5	tri_state	3-state latch output bit 5. Drives the stored latch state when /OE=LOW; high-impedance when /OE=HIGH.
15	Q4	tri_state	3-state latch output bit 4. Drives the stored latch state when /OE=LOW; high-impedance when /OE=HIGH.
16	Q3	tri_state	3-state latch output bit 3. Drives the stored latch state when /OE=LOW; high-impedance when /OE=HIGH.
17	Q2	tri_state	3-state latch output bit 2. Drives the stored latch state when /OE=LOW; high-impedance when /OE=HIGH.
18	Q1	tri_state	3-state latch output bit 1. Drives the stored latch state when /OE=LOW; high-impedance when /OE=HIGH.
19	Q0	tri_state	3-state latch output bit 0. Drives the stored latch state when /OE=LOW; high-impedance when /OE=HIGH.
20	VCC	power_in	Positive supply. Recommended 4.5 V to 5.5 V for the 74HCT573 (TTL-level) variant; absolute maximum 7 V. Bypass with a 100 nF ceramic close to the pin.

Key specifications

Parameter	Value
Manufacturer	Nexperia
Package	SOIC-20
Category	Logic
Pins	20

Ordering variants

74HCT573DD
74HCT573DPW
74HCT573DBQ

CAD (KiCad official)

Symbol: 74HCT573D
Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
3D model: SOIC-20 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Nexperia datasheet (16 pp, sha256 a2aac3ecdfa4b2e6, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF