component
74HC86D
Public Unreviewedby Ray
Nexperia Gates, SOIC-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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README
markdown74HC86D
Nexperia · Gates · SOIC-14
74HC86D from Nexperia, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Gate 1 data input A. CMOS-level logic input to the first 2-input XOR gate. |
| 2 | 1B | input | Gate 1 data input B. CMOS-level logic input to the first 2-input XOR gate. |
| 3 | 1Y | output | Gate 1 data output. XOR result of inputs 1A and 1B. Drives up to ±5.2 mA at VCC = 6.0 V. |
| 4 | 2A | input | Gate 2 data input A. CMOS-level logic input to the second 2-input XOR gate. |
| 5 | 2B | input | Gate 2 data input B. CMOS-level logic input to the second 2-input XOR gate. |
| 6 | 2Y | output | Gate 2 data output. XOR result of inputs 2A and 2B. Drives up to ±5.2 mA at VCC = 6.0 V. |
| 7 | GND | power_in | Ground reference (0 V). Common return for supply and all logic signals. |
| 8 | 3Y | output | Gate 3 data output. XOR result of inputs 3A and 3B. Drives up to ±5.2 mA at VCC = 6.0 V. |
| 9 | 3A | input | Gate 3 data input A. CMOS-level logic input to the third 2-input XOR gate. |
| 10 | 3B | input | Gate 3 data input B. CMOS-level logic input to the third 2-input XOR gate. |
| 11 | 4Y | output | Gate 4 data output. XOR result of inputs 4A and 4B. Drives up to ±5.2 mA at VCC = 6.0 V. |
| 12 | 4A | input | Gate 4 data input A. CMOS-level logic input to the fourth 2-input XOR gate. |
| 13 | 4B | input | Gate 4 data input B. CMOS-level logic input to the fourth 2-input XOR gate. |
| 14 | VCC | power_in | Positive supply voltage. Operating range 2.0 V to 6.0 V (74HC86) or 4.5 V to 5.5 V (74HCT86). Bypass with a 100 nF ceramic capacitor to GND close to the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
Ordering variants
74HC86DD74HC86DPW
CAD (KiCad official)
- Symbol:
74HC86D - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
74hc86d.step |
195 KB | You want the bare part, or you mark your own boards. |
74hc86d-etched.step |
1.9 MB | You want the part with 74HC86D already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 479 faces against 237 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (12 pp, sha256
efb3cf17b91fff76, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).