74HC74D from Nexperia, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	1RD	input	Flip-flop 1 asynchronous reset-direct input (active LOW). Drives 1Q LOW / 1Q-bar HIGH independent of clock when asserted.
2	1D	input	Flip-flop 1 data input. Value present at 1D at the LOW-to-HIGH transition of 1CP (meeting setup/hold) is stored and appears at 1Q.
3	1CP	input	Flip-flop 1 clock input, positive edge-triggered (LOW-to-HIGH). Schmitt-trigger action makes it tolerant of slow clock rise/fall times.
4	1SD	input	Flip-flop 1 asynchronous set-direct input (active LOW). Drives 1Q HIGH / 1Q-bar LOW independent of clock when asserted.
5	1Q	output	Flip-flop 1 true output. Reflects the state stored on the previous LOW-to-HIGH transition of 1CP, or is forced by 1SD/1RD.
6	1Q	output	Flip-flop 1 complement output (1Q-bar). Inverse of 1Q except when both 1SD and 1RD are asserted LOW (both outputs go HIGH per function table).
7	GND	power_in	Ground reference (0 V) for the device.
8	2Q	output	Flip-flop 2 complement output (2Q-bar). Inverse of 2Q except when both 2SD and 2RD are LOW.
9	2Q	output	Flip-flop 2 true output. Reflects the state stored on the previous LOW-to-HIGH transition of 2CP, or is forced by 2SD/2RD.
10	2SD	input	Flip-flop 2 asynchronous set-direct input (active LOW). Drives 2Q HIGH / 2Q-bar LOW independent of clock when asserted.
11	2CP	input	Flip-flop 2 clock input, positive edge-triggered (LOW-to-HIGH). Schmitt-trigger action tolerates slow edges.
12	2D	input	Flip-flop 2 data input. Value latched into flip-flop 2 on the LOW-to-HIGH edge of 2CP and presented at 2Q.
13	2RD	input	Flip-flop 2 asynchronous reset-direct input (active LOW). Drives 2Q LOW / 2Q-bar HIGH independent of clock when asserted.
14	VCC	power_in	Positive supply voltage. Operating range 2.0 V to 6.0 V for 74HC74 (4.5 V to 5.5 V for 74HCT74). Absolute maximum 7 V.

Key specifications

Parameter	Value
Manufacturer	Nexperia
Package	SOIC-14
Category	Logic
Pins	14

Ordering variants

74HC74DD
74HC74DPW
74HC74DBQ
74HC74DBZ

CAD (KiCad official)

Symbol: 74HC74D
Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
3D model: SOIC-14 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`74hc74d.step`	195 KB	You want the bare part, or you mark your own boards.
`74hc74d-etched.step`	1.5 MB	You want the part with `74HC74D` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 405 faces against 237 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Nexperia datasheet (19 pp, sha256 1e4ab9833ba6e6a3, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF