74HC595D from JSMSEMI, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	Q1	output	Parallel data output bit 1 from the 8-bit storage register. 3-state output; goes to high-impedance when OE is HIGH. Drive capability approximately ±6 mA at VCC = 4.5 V.
2	Q2	output	Parallel data output bit 2 from the 8-bit storage register. 3-state output; high-impedance when OE is HIGH.
3	Q3	output	Parallel data output bit 3 from the 8-bit storage register. 3-state output; high-impedance when OE is HIGH.
4	Q4	output	Parallel data output bit 4 from the 8-bit storage register. 3-state output; high-impedance when OE is HIGH.
5	Q5	output	Parallel data output bit 5 from the 8-bit storage register. 3-state output; high-impedance when OE is HIGH.
6	Q6	output	Parallel data output bit 6 from the 8-bit storage register. 3-state output; high-impedance when OE is HIGH.
7	Q7	output	Parallel data output bit 7 (MSB) from the 8-bit storage register. 3-state output; high-impedance when OE is HIGH.
8	GND	power_in	Ground reference (0 V).
9	Q7S	output	Serial data output tapped from the last stage of the shift register (not 3-state); used to cascade multiple 74HC595 devices. Drive capability approximately ±4 mA at VCC = 4.5 V.
10	MR	input	Master reset, active LOW. Asynchronously clears the 8-bit shift register only (does not clear the storage register). Must be held HIGH during normal shifting.
11	SHCP	input	Shift register clock input. Data on DS is shifted into the shift register on the LOW-to-HIGH transition of SHCP.
12	STCP	input	Storage register clock (latch) input. On the LOW-to-HIGH transition, the contents of the shift register are transferred to the 8-bit storage register (parallel outputs).
13	OE	input	Output enable, active LOW. When HIGH, parallel outputs Q0..Q7 go to high-impedance OFF-state. Does not affect Q7S or the register contents.
14	DS	input	Serial data input. Sampled on the LOW-to-HIGH transition of SHCP and shifted into stage 0 of the shift register.
15	Q0	output	Parallel data output bit 0 (LSB) from the 8-bit storage register. 3-state output; high-impedance when OE is HIGH.
16	VCC	power_in	Supply voltage. Operating range 2.0 V to 6.0 V (74HC595); recommended typical 5.0 V. Bypass with a 100 nF ceramic capacitor to GND close to the pin.

Key specifications

Parameter	Value
Manufacturer	JSMSEMI
Package	SOP-16
Category	LED-drv
Pins	16

Ordering variants

74HC595DD
74HC595DPW
74HC595DBQ
74HC595DBZ

CAD (KiCad official)

Symbol: 74HC595D
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOP-16 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`74hc595d.step`	217 KB	You want the bare part, or you mark your own boards.
`74hc595d-etched.step`	2.1 MB	You want the part with `74HC595D` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 530 faces against 267 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: JSMSEMI datasheet (21 pp, sha256 fa24207e780cd8c4, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF