74HC595A from Shenzhen Fuman, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	Q1	output	Parallel data output bit 1 from the 8-bit storage register. Low-level / high-impedance output; sinks 63-75 mA typical at VDD=5.0 V for direct LED drive.
2	Q2	output	Parallel data output bit 2 from the 8-bit storage register. Low-level / high-impedance output; sinks 63-75 mA typical at VDD=5.0 V.
3	Q3	output	Parallel data output bit 3 from the 8-bit storage register. Low-level / high-impedance output; sinks 63-75 mA typical at VDD=5.0 V.
4	Q4	output	Parallel data output bit 4 from the 8-bit storage register. Low-level / high-impedance output; sinks 63-75 mA typical at VDD=5.0 V.
5	Q5	output	Parallel data output bit 5 from the 8-bit storage register. Low-level / high-impedance output; sinks 63-75 mA typical at VDD=5.0 V.
6	Q6	output	Parallel data output bit 6 from the 8-bit storage register. Low-level / high-impedance output; sinks 63-75 mA typical at VDD=5.0 V.
7	Q7	output	Parallel data output bit 7 (MSB) from the 8-bit storage register. Low-level / high-impedance output; sinks 63-75 mA typical at VDD=5.0 V.
8	GND	power_in	Logic ground reference (0 V). Common return for VDD and all output sink currents.
9	Q7'	output	Serial data output (last stage of the 8-bit shift register). Used to cascade multiple 74HC595A devices; drive capability IOH7=-20 to -32 mA, IOL7=20 to 32 mA at VDD=5.0 V.
10	NC	unconnected	No connect. Leave floating; the datasheet marks this pin as 悬空脚 (unconnected).
11	SCK	input	Shift-register clock input. Data on SER is shifted into the 8-bit shift register on the rising edge of SCK. Maximum fCLOCK ~30 MHz at VDD=5.0 V.
12	RCK	input	Storage-register (latch) clock input. While RCK is high, the shift-register contents are transferred to the storage register that drives Q0-Q7.
13	NC	unconnected	No connect. Leave floating; the datasheet marks this pin as 悬空脚 (unconnected).
14	SER	input	Serial data input to the 8-bit shift register. Data is sampled and shifted on the rising edge of SCK. VIH >= 3.2 V, VIL <= 1.8 V at VDD=5.0 V.
15	Q0	output	Parallel data output bit 0 (LSB) from the 8-bit storage register. Low-level / high-impedance output; sinks 63-75 mA typical at VDD=5.0 V.
16	VDD	power_in	Logic supply voltage. Operating range 3.0-5.5 V (typical 5.0 V); absolute maximum 7.0 V. Bypass locally to GND with a 0.1 uF ceramic capacitor.

Key specifications

Parameter	Value
Manufacturer	Shenzhen Fuman
Package	SOIC-16
Category	Logic
Pins	16

CAD (KiCad official)

Symbol: 74HC595A
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOIC-16 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`74hc595a.step`	217 KB	You want the bare part, or you mark your own boards.
`74hc595a-etched.step`	2.1 MB	You want the part with `74HC595A` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 524 faces against 267 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Shenzhen Fuman datasheet (5 pp, sha256 7839357fddf4f4ef, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF