74HC4053M from HGSEMI, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	Y1B	bidirectional	Independent analog I/O of channel B, switch position 1. Bidirectional analog pin selectable to Zb when Sb=H and E(bar)=L.
2	Y0B	bidirectional	Independent analog I/O of channel B, switch position 0. Bidirectional analog pin selectable to Zb when Sb=L and E(bar)=L.
3	Y1C	bidirectional	Independent analog I/O of channel C, switch position 1. Bidirectional analog pin selectable to Zc when Sc=H and E(bar)=L.
4	ZC	bidirectional	Common analog I/O of channel C. Routed to Y0C or Y1C via Sc when enable E(bar)=L. Ron typ ~115 Ω at VDD-VEE=5 V.
5	Y0C	bidirectional	Independent analog I/O of channel C, switch position 0. Bidirectional analog pin selectable to Zc when Sc=L and E(bar)=L.
6	E	input	Active-low enable input (E-bar). When LOW, one switch per section is selected by Sn; when HIGH all switches are OFF (high impedance). Digital input referenced to VDD/VSS.
7	VEE	power_in	Negative analog supply for the switch channels. Range -6 V to 0 V; may be tied to VSS for single-supply digital mux operation. VDD-VEE ≤ 9 V.
8	VSS	power_in	Ground / digital logic negative supply. Reference for the Sn and E(bar) digital control inputs.
9	SC	input	Channel C select input. Sc=L selects Y0C→Zc, Sc=H selects Y1C→Zc when E(bar)=L. Digital input referenced to VDD/VSS.
10	SB	input	Channel B select input. Sb=L selects Y0B→Zb, Sb=H selects Y1B→Zb when E(bar)=L.
11	SA	input	Channel A select input. Sa=L selects Y0A→Za, Sa=H selects Y1A→Za when E(bar)=L.
12	Y0A	bidirectional	Independent analog I/O of channel A, switch position 0. Bidirectional analog pin selectable to Za when Sa=L and E(bar)=L.
13	Y1A	bidirectional	Independent analog I/O of channel A, switch position 1. Bidirectional analog pin selectable to Za when Sa=H and E(bar)=L.
14	ZA	bidirectional	Common analog I/O of channel A. Routed to Y0A or Y1A via Sa when enable E(bar)=L.
15	ZB	bidirectional	Common analog I/O of channel B. Routed to Y0B or Y1B via Sb when enable E(bar)=L.
16	VDD	power_in	Positive supply voltage. Recommended 3.0-9.0 V (typ 5.0 V). VDD-VEE must not exceed 9 V.

Key specifications

Parameter	Value
Manufacturer	HGSEMI
Package	SOP-16
Category	Logic
Pins	16

Ordering variants

74HC4053MM/TR
74HC4053MN
74HC4053MMT/TR
74HC4053MMS/TR
74HC4053MLQ/TR

CAD (KiCad official)

Symbol: 74HC4053M
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOP-16 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`74hc4053m.step`	217 KB	You want the bare part, or you mark your own boards.
`74hc4053m-etched.step`	2.2 MB	You want the part with `74HC4053M` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 574 faces against 267 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: HGSEMI datasheet (14 pp, sha256 4dd2103c9b371c7c, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF