74HC4052MT from HGSEMI, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	Y0B	bidirectional	Bank B independent input/output channel 0. Connects to ZB when A1=L, A0=L and E=L. Analog signal range VEE to VDD.
2	Y2B	bidirectional	Bank B independent input/output channel 2. Connects to ZB when A1=H, A0=L and E=L. Analog signal range VEE to VDD.
3	ZB	bidirectional	Bank B common input/output. Routed to the selected Y0B-Y3B channel when E=L. Analog signal range VEE to VDD.
4	Y3B	bidirectional	Bank B independent input/output channel 3. Connects to ZB when A1=H, A0=H and E=L. Analog signal range VEE to VDD.
5	Y1B	bidirectional	Bank B independent input/output channel 1. Connects to ZB when A1=L, A0=H and E=L. Analog signal range VEE to VDD.
6	E	input	Active-low enable input. When E=L the mux passes signals per A0/A1; when E=H all channels are in a high-impedance off state (IOZY typ. <200 nA).
7	VEE	power_in	Negative analog supply for the switch pass-transistors, sets the lower limit of the analog signal range. Recommended VEE = -6.0 V to 0 V; for pure digital-mux use tie VEE to VSS (GND).
8	VSS	power_in	Ground / digital return for the A0, A1, E logic inputs.
9	A1	input	Digital select input, bit 1 (MSB) of the 2-bit channel-select code for both banks. Referenced to VDD/VSS.
10	A0	input	Digital select input, bit 0 (LSB) of the 2-bit channel-select code for both banks. Referenced to VDD/VSS.
11	Y3A	bidirectional	Bank A independent input/output channel 3. Connects to ZA when A1=H, A0=H and E=L. Analog signal range VEE to VDD.
12	Y0A	bidirectional	Bank A independent input/output channel 0. Connects to ZA when A1=L, A0=L and E=L. Analog signal range VEE to VDD.
13	ZA	bidirectional	Bank A common input/output. Routed to the selected Y0A-Y3A channel when E=L. Analog signal range VEE to VDD.
14	Y1A	bidirectional	Bank A independent input/output channel 1. Connects to ZA when A1=L, A0=H and E=L. Analog signal range VEE to VDD.
15	Y2A	bidirectional	Bank A independent input/output channel 2. Connects to ZA when A1=H, A0=L and E=L. Analog signal range VEE to VDD.
16	VDD	power_in	Positive supply for the digital control logic and upper analog rail. Recommended VDD = 3.0 V to 9.0 V (5.0 V typical); VDD-VEE must not exceed 9 V (12 V absolute max).

Key specifications

Parameter	Value
Manufacturer	HGSEMI
Package	TSSOP-16
Category	Comm/UART
Pins	16

Ordering variants

74HC4052MT/TR
74HC4052MTN
74HC4052MTM/TR
74HC4052MTMS/TR
74HC4052MTLQ/TR

CAD (KiCad official)

Symbol: 74HC4052MT
Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
3D model: TSSOP-16 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`74hc4052mt.step`	205 KB	You want the bare part, or you mark your own boards.
`74hc4052mt-etched.step`	2.2 MB	You want the part with `74HC4052MT` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 565 faces against 255 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: HGSEMI datasheet (13 pp, sha256 c10511caf4ff602c, retrieved 2026-08-17, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF