74HC4052LQ from HGSEMI, in a QFN-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	Y0B	bidirectional	Mux B independent analog I/O channel 0. Bidirectional analog switch terminal; connected to ZB when A1=L, A0=L and E=L. RON typ 80 Ω at VDD-VEE=9 V.
2	Y2B	bidirectional	Mux B independent analog I/O channel 2. Connected to ZB when A1=H, A0=L and E=L.
3	ZB	bidirectional	Mux B common analog I/O. Routed to one of Y0B..Y3B according to A1/A0 when E=L; high-impedance when E=H.
4	Y3B	bidirectional	Mux B independent analog I/O channel 3. Connected to ZB when A1=H, A0=H and E=L.
5	Y1B	bidirectional	Mux B independent analog I/O channel 1. Connected to ZB when A1=L, A0=H and E=L.
6	E	input	Active-low common enable. When E=L, one selected channel per mux (A/B) is turned on; when E=H all switches are OFF (high impedance) regardless of A0/A1.
7	VEE	power_in	Negative analog supply. Sets the lower rail for the analog switch pass range (VEE ≤ VI/O ≤ VDD). Typical range -6 V to 0 V; VDD-VEE ≤ 9 V recommended.
8	VSS	power_in	Digital ground (0 V reference for A0, A1, E logic inputs). Tie to VEE when used as a purely digital 4-to-1 mux/demux.
9	A1	input	Channel-select address bit 1 (MSB). Digital input referenced VSS..VDD; selects one of four channels per mux together with A0.
10	A0	input	Channel-select address bit 0 (LSB). Digital input referenced VSS..VDD; selects one of four channels per mux together with A1.
11	Y3A	bidirectional	Mux A independent analog I/O channel 3. Connected to ZA when A1=H, A0=H and E=L.
12	Y0A	bidirectional	Mux A independent analog I/O channel 0. Connected to ZA when A1=L, A0=L and E=L.
13	ZA	bidirectional	Mux A common analog I/O. Routed to one of Y0A..Y3A according to A1/A0 when E=L; high-impedance when E=H.
14	Y1A	bidirectional	Mux A independent analog I/O channel 1. Connected to ZA when A1=L, A0=H and E=L.
15	Y2A	bidirectional	Mux A independent analog I/O channel 2. Connected to ZA when A1=H, A0=L and E=L.
16	VDD	power_in	Positive supply. Recommended 3.0-9.0 V (typ 5.0 V); VDD-VEE ≤ 9 V. Sets the upper rail for both the digital logic and the analog switch pass range.

Key specifications

Parameter	Value
Manufacturer	HGSEMI
Package	QFN-16(3x3)
Category	Interface
Pins	16

Ordering variants

74HC4052LQ
74HC4052LQ/TR
74HC4052LQN
74HC4052LQM/TR
74HC4052LQMT/TR
74HC4052LQMS/TR

CAD (KiCad official)

Symbol: 74HC4052LQ
Footprint: Package_DFN_QFN:MPS_QFN-16_3x3mm_P0.5mm
3D model: QFN-16(3x3) (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`74hc4052lq.step`	95 KB	You want the bare part, or you mark your own boards.
`74hc4052lq-etched.step`	1.8 MB	You want the part with `74HC4052LQ` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 459 faces against 104 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: HGSEMI datasheet (13 pp, sha256 c10511caf4ff602c, retrieved 2026-08-17, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF