component
74hc393d
Public Unreviewedby Ray
Nexperia Counters / Dividers, SOIC-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
README
markdown74HC393D
Nexperia · Counters / Dividers · SOIC-14
74HC393D from Nexperia, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1CP | input | Counter 1 clock input. The counter advances on the HIGH-to-LOW (falling-edge) transition of 1CP. Standard CMOS/TTL input levels; VCC = 2.0 V to 6.0 V. |
| 2 | 1MR | input | Counter 1 asynchronous master reset input, active HIGH. A HIGH on 1MR clears all four stages of counter 1 and forces 1Q0..1Q3 LOW independently of the state of 1CP. |
| 3 | 1Q0 | output | Counter 1 flip-flop output, stage 0 (LSB). Buffered CMOS output; toggles on each falling edge of 1CP. |
| 4 | 1Q1 | output | Counter 1 flip-flop output, stage 1. Buffered CMOS output; divides 1CP by 4. |
| 5 | 1Q2 | output | Counter 1 flip-flop output, stage 2. Buffered CMOS output; divides 1CP by 8. |
| 6 | 1Q3 | output | Counter 1 flip-flop output, stage 3 (MSB). Buffered CMOS output; divides 1CP by 16. |
| 7 | GND | power_in | Ground reference (0 V) for both counters and the output buffers. |
| 8 | 2Q3 | output | Counter 2 flip-flop output, stage 3 (MSB). Buffered CMOS output; divides 2CP by 16. |
| 9 | 2Q2 | output | Counter 2 flip-flop output, stage 2. Buffered CMOS output; divides 2CP by 8. |
| 10 | 2Q1 | output | Counter 2 flip-flop output, stage 1. Buffered CMOS output; divides 2CP by 4. |
| 11 | 2Q0 | output | Counter 2 flip-flop output, stage 0 (LSB). Buffered CMOS output; toggles on each falling edge of 2CP. |
| 12 | 2MR | input | Counter 2 asynchronous master reset input, active HIGH. A HIGH on 2MR clears all four stages of counter 2 and forces 2Q0..2Q3 LOW independently of the state of 2CP. |
| 13 | 2CP | input | Counter 2 clock input. The counter advances on the HIGH-to-LOW (falling-edge) transition of 2CP. Standard CMOS/TTL input levels; VCC = 2.0 V to 6.0 V. |
| 14 | VCC | power_in | Positive supply voltage. Operating range 2.0 V to 6.0 V (74HC393); TTL-input variant 74HCT393 typically 4.5 V to 5.5 V. Decouple to GND with a 100 nF ceramic close to the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
Ordering variants
74HC393DD74HC393DPW74HC393DBQ
CAD (KiCad official)
- Symbol:
74HC393D - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (None pp, sha256
42d273f87d2e5d89, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).