74HC165PW from Nexperia, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PL	input	Asynchronous parallel load input (active LOW). When PL is LOW, data from D0-D7 is loaded into the shift register asynchronously; when HIGH, data enters serially at DS on rising CP edges.
2	CP	input	Clock input, LOW-to-HIGH edge-triggered. Serial data is shifted on rising edges when CE is LOW and PL is HIGH. Max fmax typically 51 MHz at VCC=4.5 V.
3	D4	input	Parallel data input bit 4. Loaded into internal shift register stage Q4 when PL is asserted LOW.
4	D5	input	Parallel data input bit 5. Loaded into internal shift register stage Q5 when PL is asserted LOW.
5	D6	input	Parallel data input bit 6. Loaded into internal shift register stage Q6 when PL is asserted LOW.
6	D7	input	Parallel data input bit 7 (last stage). Loaded into internal shift register stage Q7 when PL is asserted LOW and appears at Q7 output.
7	Q7	output	Complementary (inverted) serial output from the last shift-register stage. Provides logical complement of Q7.
8	GND	power_in	Ground reference (0 V).
9	Q7	output	Serial output from the last stage of the shift register. Cascade this pin to DS of a downstream 74HC165 for wider registers.
10	DS	input	Serial data input. Sampled on the LOW-to-HIGH CP edge when CE is LOW and PL is HIGH; drives the first register stage.
11	D0	input	Parallel data input bit 0. Loaded into internal shift register stage Q0 when PL is asserted LOW.
12	D1	input	Parallel data input bit 1. Loaded into internal shift register stage Q1 when PL is asserted LOW.
13	D2	input	Parallel data input bit 2. Loaded into internal shift register stage Q2 when PL is asserted LOW.
14	D3	input	Parallel data input bit 3. Loaded into internal shift register stage Q3 when PL is asserted LOW.
15	CE	input	Clock enable input (active LOW). When CE is LOW, data is shifted on CP rising edges; when HIGH, CP is disabled and the register holds its state.
16	VCC	power_in	Positive supply voltage. 2.0 V to 6.0 V for 74HC165; 4.5 V to 5.5 V for 74HCT165.

Key specifications

Parameter	Value
Manufacturer	Nexperia
Package	TSSOP-16
Category	Logic
Pins	16

Ordering variants

74HC165PW
74HC165PWD
74HC165PWBQ

CAD (KiCad official)

Symbol: 74HC165PW
Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
3D model: TSSOP-16 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`74hc165pw.step`	205 KB	You want the bare part, or you mark your own boards.
`74hc165pw-etched.step`	2.1 MB	You want the part with `74HC165PW` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 529 faces against 255 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Nexperia datasheet (18 pp, sha256 376fad78107f38d0, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF