component
74HC164PW
Public Unreviewedby Ray
Nexperia Shifting Register, TSSOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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README
markdown74HC164PW
Nexperia · Shifting Register · TSSOP-14
74HC164PW from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DSA | input | Gated serial data input A. AND-combined with DSB to feed the first flip-flop; either input can serve as an active-HIGH enable for the other. Data must meet set-up/hold before the LOW-to-HIGH CP transition. |
| 2 | DSB | input | Gated serial data input B. AND-combined with DSA to feed the first flip-flop; either input can serve as an active-HIGH enable for the other. |
| 3 | Q0 | output | Parallel data output, bit 0 (first stage of the shift register). CMOS push-pull output. |
| 4 | Q1 | output | Parallel data output, bit 1. CMOS push-pull output. |
| 5 | Q2 | output | Parallel data output, bit 2. CMOS push-pull output. |
| 6 | Q3 | output | Parallel data output, bit 3. CMOS push-pull output. |
| 7 | GND | power_in | Ground reference (0 V). |
| 8 | CP | input | Clock input. Data is shifted on the LOW-to-HIGH edge (edge-triggered). Maximum frequency typically 78 MHz at Vcc=5 V. |
| 9 | MR | input | Master reset input, active LOW. Asynchronously clears the register and forces all Q outputs LOW, independent of CP. |
| 10 | Q4 | output | Parallel data output, bit 4. CMOS push-pull output. |
| 11 | Q5 | output | Parallel data output, bit 5. CMOS push-pull output. |
| 12 | Q6 | output | Parallel data output, bit 6. CMOS push-pull output. |
| 13 | Q7 | output | Parallel data output, bit 7 (last stage of the shift register). CMOS push-pull output. |
| 14 | VCC | power_in | Positive supply voltage. 74HC164: 2.0 to 6.0 V (recommended). 74HCT164: 4.5 to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
Ordering variants
74HC164PW74HC164PWD74HC164PWBQ
CAD (KiCad official)
- Symbol:
74HC164PW - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
74hc164pw.step |
194 KB | You want the bare part, or you mark your own boards. |
74hc164pw-etched.step |
1.9 MB | You want the part with 74HC164PW already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 500 faces against 237 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (16 pp, sha256
aa299aaeb852d99f, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).