component
74HC125D
Public Unreviewedby Ray
Nexperia Buffer/Driver/Transceiver, SOIC-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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README
markdown74HC125D
Nexperia · Buffer/Driver/Transceiver · SOIC-14
74HC125D from Nexperia, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1OE | input | Output enable input for buffer 1 (active LOW). A LOW enables buffer 1 to pass 1A to 1Y; a HIGH places 1Y into high-impedance state. |
| 2 | 1A | input | Data input for buffer 1. CMOS-level input (74HC125) or TTL-level input (74HCT125); VI range 0 V to VCC. |
| 3 | 1Y | tri_state | Data output for buffer 1. 3-state output; drives typically ±6 mA at VCC = 4.5 V. High-Z when 1OE is HIGH. |
| 4 | 2OE | input | Output enable input for buffer 2 (active LOW). A LOW enables 2A to 2Y; a HIGH places 2Y into high-impedance state. |
| 5 | 2A | input | Data input for buffer 2. CMOS/TTL logic input; VI range 0 V to VCC. |
| 6 | 2Y | tri_state | Data output for buffer 2. 3-state output controlled by 2OE. |
| 7 | GND | power_in | Ground reference (0 V). |
| 8 | 3Y | tri_state | Data output for buffer 3. 3-state output controlled by 3OE. |
| 9 | 3A | input | Data input for buffer 3. CMOS/TTL logic input; VI range 0 V to VCC. |
| 10 | 3OE | input | Output enable input for buffer 3 (active LOW). A LOW enables 3A to 3Y; a HIGH places 3Y into high-impedance state. |
| 11 | 4Y | tri_state | Data output for buffer 4. 3-state output controlled by 4OE. |
| 12 | 4A | input | Data input for buffer 4. CMOS/TTL logic input; VI range 0 V to VCC. |
| 13 | 4OE | input | Output enable input for buffer 4 (active LOW). A LOW enables 4A to 4Y; a HIGH places 4Y into high-impedance state. |
| 14 | VCC | power_in | Positive supply voltage. 74HC125: 2.0 V to 6.0 V. 74HCT125: 4.5 V to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
Ordering variants
74HC125DD74HC125DPW
CAD (KiCad official)
- Symbol:
74HC125D - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
74hc125d.step |
195 KB | You want the bare part, or you mark your own boards. |
74hc125d-etched.step |
1.8 MB | You want the part with 74HC125D already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 473 faces against 237 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (13 pp, sha256
3b5da3a3dcae2624, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).