74HC123D from Nexperia, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	1A	input	Negative-edge triggered input for monostable 1 (Schmitt-trigger input). A HIGH-to-LOW transition on 1A triggers a pulse when 1B is HIGH and 1RD is HIGH.
2	1B	input	Positive-edge triggered input for monostable 1 (Schmitt-trigger input). A LOW-to-HIGH transition on 1B triggers a pulse when 1A is LOW and 1RD is HIGH.
3	1RD	input	Direct reset (active LOW) and positive-edge triggered input for monostable 1. Driving LOW terminates the output pulse; a LOW-to-HIGH transition can also trigger a pulse.
4	1Q	output	Active LOW inverted output of monostable 1. Complement of 1Q; goes HIGH during the timed output pulse.
5	2Q	output	Active HIGH output of monostable 2. Goes HIGH for the programmed pulse width when triggered.
6	2CEXT	passive	External timing capacitor connection for monostable 2. Connect CEXT between this pin and 2REXT/CEXT (pin 7); pulse width = K x REXT x CEXT.
7	2REXT/CEXT	passive	External timing resistor and capacitor connection for monostable 2. REXT ties from this pin to VCC (2 kOhm to 1000 kOhm typical); CEXT ties from this pin to 2CEXT (pin 6).
8	GND	power_in	Ground reference (0 V).
9	2A	input	Negative-edge triggered input for monostable 2 (Schmitt-trigger input). A HIGH-to-LOW transition on 2A triggers a pulse when 2B is HIGH and 2RD is HIGH.
10	2B	input	Positive-edge triggered input for monostable 2 (Schmitt-trigger input). A LOW-to-HIGH transition on 2B triggers a pulse when 2A is LOW and 2RD is HIGH.
11	2RD	input	Direct reset (active LOW) and positive-edge triggered input for monostable 2. Driving LOW terminates the output pulse; a LOW-to-HIGH transition can also trigger a pulse.
12	2Q	output	Active LOW inverted output of monostable 2. Complement of 2Q; goes HIGH during the timed output pulse.
13	1Q	output	Active HIGH output of monostable 1. Goes HIGH for the programmed pulse width when triggered.
14	1CEXT	passive	External timing capacitor connection for monostable 1. Connect CEXT between this pin and 1REXT/CEXT (pin 15); pulse width = K x REXT x CEXT.
15	1REXT/CEXT	passive	External timing resistor and capacitor connection for monostable 1. REXT ties from this pin to VCC (2 kOhm to 1000 kOhm typical); CEXT ties from this pin to 1CEXT (pin 14).
16	VCC	power_in	Supply voltage. 2.0 V to 6.0 V (74HC123) or 4.5 V to 5.5 V (74HCT123). Absolute maximum 7 V.

Key specifications

Parameter	Value
Manufacturer	Nexperia
Package	SOIC-16
Category	Logic
Pins	16

Ordering variants

74HC123DD
74HC123DPW
74HC123DBQ

CAD (KiCad official)

Symbol: 74HC123D
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOIC-16 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`74hc123d.step`	217 KB	You want the bare part, or you mark your own boards.
`74hc123d-etched.step`	2.0 MB	You want the part with `74HC123D` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 513 faces against 267 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Nexperia datasheet (20 pp, sha256 0b5ba7a32cf4830a, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF