π120E30 from 2Pai Semi, in a SOIC-8-N. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDD1	power_in	Supply voltage for isolator Side 1. 3.0 V to 5.5 V operating range; 2.75 V typical undervoltage lockout rising threshold. Bypass to GND1 with 0.1 µF-10 µF low-ESR ceramic close to the pin.
2	VIA	input	Logic input for channel A (Side 1). CMOS input, VIH ≥ 0.7·VDD1, VIL ≤ 0.3·VDD1. Absolute max −0.5 V to VDD1 + 0.5 V. Drives isolated logic output VOA on Side 2.
3	VIB	input	Logic input for channel B (Side 1). CMOS input, VIH ≥ 0.7·VDD1, VIL ≤ 0.3·VDD1. Drives isolated logic output VOB on Side 2. Both π120 channels are forward (Side 1 → Side 2).
4	GND1	power_in	Ground reference for isolator Side 1. Return for VDD1 bypass and for VIA/VIB input signals. Isolated from GND2 across the on-die iDivider capacitive barrier.
5	GND2	power_in	Ground reference for isolator Side 2. Return for VDD2 bypass and for VOA/VOB output signals. Isolated from GND1 (3.0 kVrms withstand for the E3x variant).
6	VOB	output	Logic output for channel B (Side 2), mirrors VIB across the isolation barrier. Push-pull CMOS output rated ±10 mA absolute max, recommended ±6 mA. Fail-safe LOW when VDD1 unpowered (E30 suffix).
7	VOA	output	Logic output for channel A (Side 2), mirrors VIA across the isolation barrier. Push-pull CMOS output rated ±10 mA absolute max, recommended ±6 mA. Fail-safe LOW when VDD1 unpowered (E30 suffix).
8	VDD2	power_in	Supply voltage for isolator Side 2. 3.0 V to 5.5 V; independent of VDD1 so this pin performs the 3 V ↔ 5 V level translation. Bypass to GND2 with 0.1 µF-10 µF low-ESR ceramic close to the pin.

Key specifications

Parameter	Value
Manufacturer	2Pai Semi
Package	SOIC-8-N
Category	PMIC
Pins	8

Ordering variants

π120E30π120E31
π120E30π120E31Q
π120E30
π120E30Q
π120E30π120E61
π120E30π120E61Q
π120E30π120E60
π120E30π120E60Q

CAD (KiCad official)

Symbol: π120E30
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8-N (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`120e30.step`	122 KB	You want the bare part, or you mark your own boards.
`120e30-etched.step`	1.6 MB	You want the part with `120E30` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 399 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: 2Pai Semi datasheet (18 pp, sha256 46f1f75769a4de29, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF