board
OCuLink Riser for the Supermicro AIOM Slot
Public Unreviewedby John Lauer
Passive OCP NIC 3.0 SFF card that breaks a Supermicro AIOM slot's PCIe x16 into four OCuLink 4i ports (4 x4, Gen4): 6-layer, 85 ohm, length-matched, DRC-clean KiCad project with Gerbers, BOM and CPL.
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clips/README.md+12@@ -16,6 +16,7 @@ The whole build, filmed off the screen while Claude worked in Adom Hydrogen, cut | [10. Debugging the field solver](#10-debugging-the-field-solver) | 7:06 to 7:53 | The board waits in KiCad while Claude finds why the current solve will not converge | | [11. The via ring, a finer solve, and silkscreen](#11-the-via-ring-a-finer-solve-and-silkscreen) | 7:59 to 8:45 | Why the current solve failed, the 0.1 mm re-solve, silkscreen layout on both faces | | [12. Current, thermal, net tour, silkscreen and 3D](#12-current-thermal-net-tour-silkscreen-and-3d) | 8:40 to 9:26 | The current and thermal checks pass, the pour walkthrough, clean silkscreen, the 3D board |+| [13. Analysis drawings, export and the finish line](#13-analysis-drawings-export-and-the-finish-line) | 9:32 to 10:17 | Heat and current maps, Gerbers/BOM/CPL exported and checked, renders, the finish step | ## 1. The request and the research @@ -154,3 +155,14 @@ The whole build, filmed off the screen while Claude worked in Adom Hydrogen, cut - The pour walkthrough in KiCad lights each poured net on its own. - Silkscreen: zero coverage errors, zero missing obstacles, zero collisions. - The board in KiCad's 3D viewer, with the OCuLink connectors, gold fingers and labelled test points.++## 13. Analysis drawings, export and the finish line++<video controls preload="metadata" width="1080" poster="clips/clip-13-poster.jpg" src="clips/clip-13.mp4"></video>++[Download clip 13](clips/clip-13.mp4) (2 min 53 s, 16x, narrated, filmed from the chat window)++- The analysis drawings: current density, heat flow per layer and temperature rise. About 0.1 A on the card; peak rise 0.066 C.+- The export: Gerbers for all six copper layers plus silkscreen, mask, paste and edge cuts, drill files, pick-and-place and BOM, each read back and checked against the board.+- Export check: 6 copper layers, 820 plated holes, 8 unplated holes (the OCuLink alignment pegs), CPL and BOM matching all 38 placed parts.+- Renders of the finished card for the project page, then the timeline reaches step 18, the finish line.
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