board
OCuLink Riser for the Supermicro AIOM Slot
Public Unreviewedby John Lauer
Passive OCP NIC 3.0 SFF card that breaks a Supermicro AIOM slot's PCIe x16 into four OCuLink 4i ports (4 x4, Gen4): 6-layer, 85 ohm, length-matched, DRC-clean KiCad project with Gerbers, BOM and CPL.
← Commit history
clips/README.md+13@@ -8,6 +8,7 @@ The whole build, filmed off the screen while Claude worked in Adom Hydrogen, cut | [2. Routing the high-speed lanes](#2-routing-the-high-speed-lanes) | 0:52 to 1:38 | The netlist, 36 differential pairs routed and length-tuned, the slow-net router, the connector model | | [3. Design rule check and the design record](#3-design-rule-check-and-the-design-record) | 1:38 to 2:25 | KiCad DRC, fixes at the source, a pause to ask before taking over the screen, skew results | | [4. Scan chain, parts and sourcing](#4-scan-chain-parts-and-sourcing) | 2:25 to 3:12 | The router converging, the outline fix, the OCP scan chain, new component pages, live stock |+| [5. Design rules and routing closed](#5-design-rules-and-routing-closed) | 3:12 to 3:59 | Steps declared on the timeline, JLCPCB 6-layer rules, every net routed, final DRC and cleanup | ## 1. The request and the research @@ -57,3 +58,15 @@ The whole build, filmed off the screen while Claude worked in Adom Hydrogen, cut - The SN74LV165A shift register is the card's OCP 3.0 scan chain: it reports the card's status and details to the server, alongside the present pins that signal a card is installed. - Two parts get new Adom wiki component pages, including the OCuLink receptacle, with a provenance record marking which files are AI-generated. - Live Mouser and DigiKey stock checks for the new capacitor and the status LED, and a bill of materials of orderable parts.++## 5. Design rules and routing closed++<video controls preload="metadata" width="1080" poster="clips/clip-05-poster.jpg" src="clips/clip-05.mp4"></video>++[Download clip 5](clips/clip-05.mp4) (2 min 53 s, 16x, narrated)++- One follow-up prompt here: declare each adom-aiflow step as you go. The timeline moves to step 2, design rules.+- JLCPCB 6-layer rules: 0.09 mm trace and space, 0.15 mm drill, 0.2 mm edge clearance, plus an exception for the OCuLink connector's alignment pegs from Amphenol's land pattern.+- The router closes: every low-speed net connected, ground vias fanned out, final board build and DRC.+- A second note: update adom-aiflow, whose latest version covers high-speed boards where the AI brings its own router into the flow.+- The final check finds dangling copper stubs and a bug in the cleanup step that deleted a whole diagonal segment instead of trimming it; Claude fixes the pruning and rebuilds.
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