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Clip 6

John Lauer ·50b39328b7 ·7d ago ·parent 6752343
3 files changed +12
clips/README.md+12
@@ -9,6 +9,7 @@ The whole build, filmed off the screen while Claude worked in Adom Hydrogen, cut | [3. Design rule check and the design record](#3-design-rule-check-and-the-design-record) | 1:38 to 2:25 | KiCad DRC, fixes at the source, a pause to ask before taking over the screen, skew results | | [4. Scan chain, parts and sourcing](#4-scan-chain-parts-and-sourcing) | 2:25 to 3:12 | The router converging, the outline fix, the OCP scan chain, new component pages, live stock | | [5. Design rules and routing closed](#5-design-rules-and-routing-closed) | 3:12 to 3:59 | Steps declared on the timeline, JLCPCB 6-layer rules, every net routed, final DRC and cleanup |+| [6. The board opens in KiCad](#6-the-board-opens-in-kicad) | 3:59 to 4:45 | Last routing fixes, the real board in KiCad, parts staged for placement |  ## 1. The request and the research @@ -70,3 +71,14 @@ The whole build, filmed off the screen while Claude worked in Adom Hydrogen, cut - The router closes: every low-speed net connected, ground vias fanned out, final board build and DRC. - A second note: update adom-aiflow, whose latest version covers high-speed boards where the AI brings its own router into the flow. - The final check finds dangling copper stubs and a bug in the cleanup step that deleted a whole diagonal segment instead of trimming it; Claude fixes the pruning and rebuilds.++## 6. The board opens in KiCad++<video controls preload="metadata" width="1080" poster="clips/clip-06-poster.jpg" src="clips/clip-06.mp4"></video>++[Download clip 6](clips/clip-06.mp4) (2 min 53 s, 16x, narrated)++- Last fixes to the routing script: a wake signal is re-routed on its own layers so it never crosses the high-speed lanes.+- KiCad opens with the real board: gold fingers along the bottom edge, the OCuLink connectors along the top, length-tuned pairs between them through the copper pours.+- The small parts are staged beside the board: the scan chain chip, its resistors, the status LED and the decoupling capacitors.+- The components and libraries steps check that every part has a footprint and a 3D model before placement.
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