OCuLink Riser for the Supermicro AIOM Slot

@@ -14,6 +14,7 @@ The whole build, filmed off the screen while Claude worked in Adom Hydrogen, cut | [8. Routing lands live](#8-routing-lands-live) | 5:33 to 6:19 | 169 traces landed one at a time in KiCad, all accepted | | [9. Pours, outline and the current check](#9-pours-outline-and-the-current-check) | 6:20 to 7:06 | Routing done, pours landed and measured, the field-solved current check | | [10. Debugging the field solver](#10-debugging-the-field-solver) | 7:06 to 7:53 | The board waits in KiCad while Claude finds why the current solve will not converge |+| [11. The via ring, a finer solve, and silkscreen](#11-the-via-ring-a-finer-solve-and-silkscreen) | 7:59 to 8:45 | Why the current solve failed, the 0.1 mm re-solve, silkscreen layout on both faces |  ## 1. The request and the research @@ -129,3 +130,14 @@ The whole build, filmed off the screen while Claude worked in Adom Hydrogen, cut - The board stays on screen in KiCad; the work is in the chat behind it. - The field solver will not converge on the +3.3 V net, so Claude instruments the solver's own source: it drops floating copper islands from the DC solve and checks for current injected into unconnected cells. - From clip 11 on, the chat window is filmed as well.++## 11. The via ring, a finer solve, and silkscreen++<video controls preload="metadata" width="1080" poster="clips/clip-11-poster.jpg" src="clips/clip-11.mp4"></video>++[Download clip 11](clips/clip-11.mp4) (2 min 53 s, 16x, narrated, filmed from the chat window)++- The cause: the vias leave a 0.1 mm copper ring, which vanishes at the solver's default grid and splits the +3.3 V net in two.+- The full solve re-runs at a 0.1 mm grid; meanwhile Claude works ahead.+- Silkscreen to JLCPCB's rules (0.8 mm minimum text height), with reference labels and port legends on both faces, sized from measured text extents.+- Silkscreen renders of both faces: a description of the card on the bottom, a label on each OCuLink port on top.

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