Diode-Bridge Voltage-Controlled Attenuator

@@ -4,7 +4,9 @@ A two-layer, hand-solderable analog board that turns a 0 to 2 V control voltage  **Status: prototype draft.** No board has been built or measured. Saif's engineering review found defects to fix before fabrication (see [Known issues](#known-issues)). -![Board, top copper](images/board-top/board-top-crop.png)+![The populated board in 3D, rendered in KiCad](images/kicad/3d/3d-iso-front-left.png)++<sub>3D views use KiCad's stock part models as stand-ins (see [About the 3D views](#about-the-3d-views)). A 3D model of the populated board is in [`models/diode-vca-attenuator.glb`](models/diode-vca-attenuator.glb).</sub>  ## What it does @@ -22,13 +24,67 @@ A two-layer, hand-solderable analog board that turns a 0 to 2 V control voltage  ## Schematic -![Schematic](images/schematic/diode-vca-attenuator.png)+![Schematic](images/kicad/schematic/schematic-crisp.png)++The full sheet with its title block: [schematic-full-sheet.png](images/kicad/schematic/schematic-full-sheet.png).++## Board in 3D++![Perspective view](images/kicad/3d/3d-hero-perspective.png)++| Front right | Back |+|---|---|+| ![Isometric, front right](images/kicad/3d/3d-iso-front-right.png) | ![Isometric, back: the diode bridge, Q1 and U1](images/kicad/3d/3d-iso-back.png) |++| Top | Bottom |+|---|---|+| ![Top](images/kicad/3d/3d-top.png) | ![Bottom](images/kicad/3d/3d-bottom.png) |++| Diode bridge close-up | Front close-up |+|---|---|+| ![D1 to D4 with Q1 and U1](images/kicad/3d/3d-closeup-bridge.png) | ![U1, Q1 and the 220 uF bipolar caps](images/kicad/3d/3d-closeup-front.png) |++![Front elevation, showing part heights](images/kicad/3d/3d-front-elevation.png)++**Bare board**++| Top | Bottom | Isometric |+|---|---|---|+| ![Bare top](images/kicad/3d/bare-board-top.png) | ![Bare bottom](images/kicad/3d/bare-board-bottom.png) | ![Bare isometric](images/kicad/3d/bare-board-iso.png) |++### About the 3D views++Saif's custom footprints carry no 3D models, so these renders put KiCad's stock models on a render-only copy of the board. They are close but not exact: C1 and C2 show a polarity stripe although the real parts are bipolar, Q1's flat face direction is a guess, and the terminal block bodies are deeper than the 7 mm footprint outline. The design files in this repo were not changed. The full model table is in [images/kicad/README-visuals.md](images/kicad/README-visuals.md). -## Board+The renders do show real layout problems: C6 and C7 overlap and C7 runs under J3, R1 sits partly under J2, and R9 touches C4. With no courtyards, KiCad's DRC cannot catch any of these. -| Top copper | Bottom copper |+## Board layers++| Top copper | Bottom copper (seen from below) |+|---|---|+| ![Front copper](images/kicad/layers/layer-f-cu.png) | ![Back copper](images/kicad/layers/layer-b-cu.png) |++| Top side combined | Both copper layers |+|---|---|+| ![F.Cu, mask, silkscreen and outline](images/kicad/layers/layer-combined-top.png) | ![Front red over back blue](images/kicad/layers/layer-combined-all-copper.png) |++| Silkscreen | Fabrication layer |+|---|---|+| ![Front silkscreen](images/kicad/layers/layer-f-silkscreen.png) | ![Front fab: outlines, references, values](images/kicad/layers/layer-f-fab.png) |++| Front mask | Back mask | Outline and drills |+|---|---|---|+| ![Front mask](images/kicad/layers/layer-f-mask.png) | ![Back mask](images/kicad/layers/layer-b-mask.png) | ![Edge cuts](images/kicad/layers/layer-edge-cuts.png) |++## In KiCad++The project opened in KiCad 10.++![PCB Editor](images/kicad/gui/gui-pcb-editor.png)++| Schematic Editor | 3D Viewer | |---|---|-| ![Top](images/board-top/board-top-crop.png) | ![Bottom](images/board-bottom/board-bottom-crop.png) |+| ![Schematic Editor](images/kicad/gui/gui-schematic-editor.png) | ![3D Viewer](images/kicad/gui/gui-3d-viewer-angled.png) |  ## Simulated response (100 mVpp input) @@ -40,6 +96,14 @@ A two-layer, hand-solderable analog board that turns a 0 to 2 V control voltage | 1.5 V | -14.11 dB | -14.19 dB | -14.19 dB | | 2.0 V | -16.10 dB | -16.23 dB | -16.23 dB | +![Frequency response at each control voltage](images/charts/frequency-response.png)++| Gain vs control | Distortion vs control |+|---|---|+| ![Gain vs control voltage](images/charts/gain-vs-control.png) | ![THD vs control voltage](images/charts/thd-vs-control.png) |++![Control feedthrough](images/charts/control-feedthrough.png)+ This is small-signal only. At 12 Vpp the diodes leave their small-signal region: the model predicts just 0.83 dB of attenuation at 2 V control, with 5.69% THD. A design meant for full-scale input would scale the signal down before the diode bridge and restore the gain after it.  ## Known issues@@ -82,6 +146,8 @@ Before this board, Saif ran a simpler test: a 1 kHz RC low-pass filter with an M | `docs/` | The generated engineering review, tool failure log and calculations | | `generate_project.py`, `tools/` | The script Hydrogen wrote to generate the project | | `rc-filter-test/` | Screenshots from the earlier RC filter test |+| `images/` | Renders, layer plots, charts and KiCad screenshots used on this page |+| `models/` | 3D model of the populated board (GLB, stock part models) |  ## Manufacturing 

@@ -0,0 +1,92 @@+# KiCad 10 visuals: diode-bridge voltage-controlled attenuator++Every image here was generated from Saif Abdessayed's KiCad 10 project (`diode-vca-attenuator.kicad_pro/.kicad_sch/.kicad_pcb`) with KiCad 10.0.1 (`kicad-cli` plus the KiCad GUI) on a Windows machine. The design files in this repo were not modified. The populated 3D views come from a separate render-only copy of the board (see "What is approximate" below).++## 3D renders (`3d/`)++Raytraced with `kicad-cli pcb render --quality high`, rendered at 2400x1500, trimmed and centered on a 1920x1200 transparent canvas (except the close-ups and the hero, which fill the frame).++| File | Caption |+|---|---|+| `3d/3d-top.png` | Populated board, straight down from the top (orthographic). |+| `3d/3d-bottom.png` | Populated board from underneath: bottom copper, pads and lead ends. |+| `3d/3d-iso-front-left.png` | Isometric view from the front left: terminal blocks, TL072, bipolar caps. |+| `3d/3d-iso-front-right.png` | Isometric view from the front right. |+| `3d/3d-iso-back.png` | Isometric view from the back, showing the four 1N4148 diode bridge, Q1 and U1. |+| `3d/3d-front-elevation.png` | Low front elevation showing component heights. |+| `3d/3d-closeup-bridge.png` | Close-up of the D1 to D4 diode bridge with Q1 (current source) and U1. |+| `3d/3d-closeup-front.png` | Close-up from the front left of U1, Q1 and the 220 uF bipolar caps. |+| `3d/3d-hero-perspective.png` | Perspective hero shot with floor shadows on KiCad's default gradient background (opaque). |+| `3d/bare-board-top.png` | Bare board (unmodified PCB, no 3D models), top. |+| `3d/bare-board-bottom.png` | Bare board, bottom. |+| `3d/bare-board-iso.png` | Bare board, isometric. |++## 3D model (`../../models/`)++| File | Caption |+|---|---|+| `models/diode-vca-attenuator.glb` | Populated board as binary glTF (3.8 MB) from `kicad-cli pcb export glb`, with tracks, pads, silkscreen and solder mask; all 26 parts are present as named nodes (J1 to J4, R1 to R9, C1 to C7, D1 to D4, Q1, U1). |++## Layer plots (`layers/`)++Exported with `kicad-cli pcb export svg` (board area only, actual drill shapes, KiCad default layer colors), rendered to 2400 px wide PNG on a dark background (#14171c) with a small margin so the board outline shows. Bottom-side plots are mirrored (seen from below).++| File | Caption |+|---|---|+| `layers/layer-f-cu.png` | Front copper (red) with board outline. |+| `layers/layer-b-cu.png` | Back copper (blue), mirrored. |+| `layers/layer-f-silkscreen.png` | Front silkscreen: connector and section labels (INPUT, OUTPUT, CONTROL, +12 GND -12, DIODE BRIDGE, DIODE VCA REV A). |+| `layers/layer-f-mask.png` | Front solder mask openings. |+| `layers/layer-b-mask.png` | Back solder mask openings, mirrored. |+| `layers/layer-edge-cuts.png` | Board outline (58 x 40 mm) with drill holes. |+| `layers/layer-f-fab.png` | Front fabrication layer: part outlines, references and values. Text overlaps in places; that is how the fab layer is drawn in the source. |+| `layers/layer-combined-top.png` | Top view: F.Cu, F.Mask, F.SilkS and Edge.Cuts together. |+| `layers/layer-combined-bottom.png` | Bottom view (mirrored): B.Cu, B.Mask and Edge.Cuts. |+| `layers/layer-combined-all-copper.png` | Both copper layers overlaid (front red over back blue) with front silkscreen. |+| `layers/diode-vca-attenuator-pcb-layers.pdf` | Multi-page PDF, one page per layer (F.Cu, B.Cu, F.SilkS, B.SilkS, F.Mask, F.Fab, Edge.Cuts), each with the board outline. |++Not included as PNGs: B.SilkS (the design has no bottom silkscreen, so the plot is empty) and F.Courtyard (the custom footprints have no courtyard shapes).++## Schematic (`schematic/`)++| File | Caption |+|---|---|+| `schematic/schematic-crisp.png` | Schematic content without the drawing sheet, cropped, about 3170 x 3240 px. |+| `schematic/schematic-full-sheet.png` | Full A4 sheet with frame and title block, 4800 px wide. |+| `schematic/diode-vca-attenuator-schematic.pdf` | Vector PDF of the schematic (`kicad-cli sch export pdf`). |++## KiCad GUI screenshots (`gui/`)++Captured from the real KiCad 10.0.1 windows (2560 x 1528, native resolution), opened on the populated render copy of the project.++| File | Caption |+|---|---|+| `gui/gui-schematic-editor.png` | Schematic Editor with the whole sheet in view. |+| `gui/gui-pcb-editor.png` | PCB Editor, zoomed to fit, all layers on. |+| `gui/gui-3d-viewer-top.png` | KiCad 3D Viewer (OpenGL) from the top, with stand-in 3D models. |+| `gui/gui-3d-viewer-angled.png` | KiCad 3D Viewer tilted and rotated. |++## What is approximate++The project's custom footprint library (`libraries/AnalogVCA_THT.pretty`) has no 3D models. For the populated renders, the GLB and the 3D viewer screenshots, a render-only copy of the board was given KiCad's stock 3D models (from `${KICAD10_3DMODEL_DIR}`). These are generic stand-ins, not Saif's exact parts:++| Custom footprint (parts) | Stock model used | Placement |+|---|---|---|+| Axial_DIN0207_P10.16mm (R1 to R4, R6 to R8) | Resistor_THT R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal | offset -5.08 mm in X |+| Axial_V_P1Bottom_P10.16mm (R5), Axial_V_P1Top_P10.16mm (R9) | the same horizontal resistor, rotated 90 degrees | lies along Y on the board; "V" in these names means a vertical orientation on the board, not a standing part (the pads are 10.16 mm apart) |+| D_DO35_V_KBottom_P10.16mm (D1 to D4) | Diode_THT D_DO-35_SOD27_P10.16mm_Horizontal, rotated 90 degrees | cathode band at pad 1 (bottom), as the footprint says |+| C_Disc_P5.00mm (C3 to C5) | Capacitor_THT C_Disc_D5.0mm_W2.5mm_P5.00mm | offset -2.5 mm |+| C_Radial_D5_P2.0mm (C6, C7) | Capacitor_THT CP_Radial_D5.0mm_P2.00mm | offset -1 mm |+| Radial_Bipolar_D12.5_P5.0mm (C1, C2) | Capacitor_THT CP_Radial_D12.5mm_P5.00mm | offset -2.5 mm. The stock model is a polarized electrolytic and shows a polarity stripe; the real parts are bipolar (non-polarized) |+| DIP8_W7.62mm (U1, TL072) | Package_DIP DIP-8_W7.62mm | shifted so model pin 1 lands on pad 1 at (-3.81, -3.81) mm; the pin 1 notch matches |+| TO92_Inline_EBC (Q1, 2N3904) | Package_TO_SOT_THT TO-92_Inline_Wide | the footprint uses 2.54 mm pitch, so the Wide (2.54 mm) model is used rather than TO-92_Inline (1.27 mm). Which way the flat face points is a guess, since the footprint does not mark it |+| Terminal_1x02/1x03_P5.08mm (J1 to J4) | TerminalBlock_Phoenix MKDS-1,5-2-5.08 / MKDS-1,5-3-5.08 (horizontal) | the stock body is about 9.8 mm deep, while the custom footprint outline is 7 mm, so the bodies look bigger than the footprint outline. The real terminal brand and wire-entry direction are not specified |++All models were checked by rendering: every body sits on its own pads at the right pitch and rotation.++Things the renders show about the layout itself (from Saif's placement, not caused by the stand-in models):++- C6 and C7 (5 mm diameter radial caps) are on 4 mm centers, so their bodies overlap, and C7 runs under the J3 terminal block.+- R1 sits partly under the J2 terminal block, and R7/R8 sit close to J3.+- R9 (vertical-orientation resistor) runs next to C4's pad 1, so the two bodies touch in 3D.+- The footprints have no courtyard layer, so KiCad's courtyard DRC cannot flag these overlaps.