project
12 V to 5 V / 1 A Buck Molecule (TPS54202)
Public Unreviewedby John Lauer
An independently designed 12 V to 5 V, 1 A synchronous buck molecule (TI TPS54202), with calculations, ngspice and PSpice simulation, KiCad 10 schematic and board, and the board laid out and analysed with adom-aiflow.
← Commit history
ECAS study: Adom Fields' own hot-plug check agrees
2 files changed
+321
ecas-capacitors/README.md+9@@ -143,6 +143,15 @@ We solved two copies of the board: as built, and with C1's MPN set to the 33 µF Adom Fields sees the same thing the hot-plug simulation does: without the can's ESR, the supply leads' resonance nearly doubles. It stays under the 0.6 Ω target and Middlebrook's limit, so no fix is listed, but the margin to the target falls from about 2x to 1.15x. With the 0.22 Ω resistor, the resonance is the lowest of the three. +Adom Fields also checks a hot plug on its own: it switches the supply leads onto every capacitor at its rail bias and solves the step in time. With the same leads as our simulation (50 mΩ, 1 µH) on the 12 V rail:++| VIN hot plug, 12 V, 1 µH | Adom Fields | ngspice (this study) | Adom Fields' review |+|---|---|---|---|+| as built (47 µF can) | 13.1 V (9 % overshoot) | 13.2 V | no issue |+| C1 = 33 µF ECAS, bare | 18.8 V (56 % overshoot) | 18.9 V | **hot-plug-overshoot**: "add at least 220 µF of bulk capacitance with about 159 mΩ of ESR (an electrolytic, or a polymer part plus a series resistor)" |++Two independent tools agree within 1 %, and the layout tool reaches the same fix this study did: a polymer part plus a series resistor.+ The output rail has the same story in reverse. With the measured parts, Adom Fields counts C6 to C8 at 10.2 µF each at 5 V, and VOUT's worst point is a quarter of its target. ## Does the board get smaller?
ecas-capacitors/fields/spec-leads.jsonadded+312@@ -0,0 +1,312 @@+{+ "board": "12 V to 5 V / 1 A buck molecule (TI TPS54202 synchronous buck, 500 kHz), 28 x 20 mm, 2 layers, medium machine pins on a 24 x 16 mm grid",+ "copperUm": 17.5,+ "copperNote": "designed for 0.5 oz outer copper, the conservative end of the fab's range",+ "clearance": 0.15,+ "edgeClearance": 0.3,+ "inheritedErrors": 0,+ "fixedRefs": [+ "MP1",+ "MP2",+ "MP3",+ "MP4",+ "J1",+ "J2",+ "J3",+ "J4",+ "J5",+ "J6"+ ],+ "fixedRefsNote": "the molecule interface: four corner machine pins (GND) and six contacts on the 2 mm grid; the scaffold and the control-panel wiring depend on these positions",+ "planes": {},+ "wideNets": {+ "VIN": [+ 0.8,+ 0.5,+ 0.3+ ],+ "VOUT": [+ 0.8,+ 0.5,+ 0.3+ ],+ "SW": [+ 0.8,+ 0.5,+ 0.3+ ],+ "GND": [+ 0.8,+ 0.5,+ 0.3+ ]+ },+ "midNets": {+ "BOOT": [+ 0.3,+ 0.2+ ]+ },+ "kelvin": {+ "R3.2": "U1.1",+ "R1.1": "C6.1"+ },+ "kelvinNote": "datasheet 7.4.1: the feedback divider's ground returns to the IC GND pin on its own trace, and the top of the divider senses VOUT at the output capacitor, not along the load current path",+ "loads": {+ "VOUT": {+ "amps": 1.0,+ "maxRiseC": 10+ },+ "SW": {+ "amps": 1.0,+ "maxRiseC": 10+ },+ "GND": {+ "amps": 1.0,+ "maxRiseC": 10+ },+ "VIN": {+ "amps": 0.6,+ "maxRiseC": 10+ }+ },+ "loadsNote": "VIN is the input current at the 9 V low end of the range (5 W / 0.93 / 9 V = 0.6 A); SW carries the inductor RMS current, 1.01 A",+ "hot": {+ "U1": {+ "watts": 0.25,+ "tabNet": "GND",+ "note": "SOT-23-6 has no exposed pad: heat leaves through the pins, mostly GND (pin 1, low-side source) and VIN (pin 3)"+ },+ "L1": {+ "watts": 0.12,+ "tabNet": "VOUT"+ }+ },+ "hotNote": "U1: I^2R at the hot Rds(on) (1.4 x 148 / 78 mOhm) over the duty at 12 V: 0.15 W, plus about 0.09 W switching (15 ns edges, 500 kHz) and gate drive: 0.25 W. L1: 1.01 A RMS squared x 118 mOhm max DCR = 0.12 W.",+ "hotMaxRiseC": 55,+ "hotMaxRiseNote": "John approved 2026-09-29 (option 2, junction-based): the budget is the pin/tab rise in STILL air. U1 +44 C at its GND pin; psi_JB 33.7 C/W x 0.25 W adds about 8 C to the junction, so Tj is about ambient + 52 C: 92 C at a 40 C ambient, 33 C under the 125 C rating. L1 +41 C is inside its -40..+125 C rating including self-heating. In moving air (25 W/m2K) both are under 30 C (U1 +24, L1 +21). A 28 x 20 mm board losing 0.37 W to still air averages about +33 C even with perfect copper, so 30 C still air is area-limited, not layout-limited: adding 8 more GND vias at the nearest free spots (2.6 to 3.8 mm from U1.1) changed U1 by 0 C in the Fields solve, so they were not added.",+ "pours": [+ {+ "net": "GND",+ "outline": true,+ "layers": [+ "F.Cu",+ "B.Cu"+ ],+ "priority": 0,+ "connection": "thermal",+ "thermalGap": 0.25,+ "thermalBridge": 0.35,+ "name": "GND both layers"+ },+ {+ "net": "VIN",+ "around": [+ "J1",+ "C1.1",+ "C2.1",+ "C3.1",+ "C4.1",+ "U1.3"+ ],+ "margin": 0.5,+ "layers": [+ "F.Cu"+ ],+ "priority": 2,+ "connection": "solid",+ "name": "VIN input loop F.Cu"+ },+ {+ "net": "VOUT",+ "around": [+ "L1.2",+ "C6.1",+ "C7.1",+ "C8.1",+ "J4",+ "TP3"+ ],+ "margin": 0.5,+ "layers": [+ "F.Cu"+ ],+ "priority": 2,+ "connection": "solid",+ "name": "VOUT output F.Cu"+ },+ {+ "net": "SW",+ "layers": [+ "F.Cu"+ ],+ "priority": 3,+ "connection": "solid",+ "name": "SW node patch F.Cu (U1.2 to L1.1, widening toward the inductor)",+ "polygon": [+ [+ 113.3,+ 90.52+ ],+ [+ 113.85,+ 90.52+ ],+ [+ 114.6,+ 89.1+ ],+ [+ 118.1,+ 89.1+ ],+ [+ 118.1,+ 92.9+ ],+ [+ 114.9,+ 92.9+ ],+ [+ 113.85,+ 91.48+ ],+ [+ 113.3,+ 91.48+ ]+ ]+ }+ ],+ "poursNote": "The input hot loop (C2/C3/C4 -> U1 VIN -> U1 GND -> C GND) stays on F.Cu over an unbroken B.Cu GND; SW is a short wide trace only, never a pour, to keep the switching node's area (and its radiated field) small. Rev 2 (after the Fields solve): a small solid SW patch between U1.2 and L1.1 removes the 0.27 mm neck while keeping the node's area small; U1's GND pin gets a solid connection and three thermal vias into the B.Cu ground plane (it is the IC's main heat path); the inductor pads connect solid.",+ "notPoured": [+ "BOOT",+ "FB",+ "FBM",+ "EN",+ "VMON",+ "LED"+ ],+ "notPouredNote": "bootstrap (dv/dt), the feedback network (high impedance, keep it small and away from SW), the enable and monitor dividers; SW only as the small patch above",+ "stitchViasNote": "Two thermal vias under U1.1 (GND pin, the IC's main heat path) and one beside C4.2, placed by hand in solid GND copper clear of SW copper (the planner's thermalVias put one 0.8 mm via inside the SOT-23 pad).",+ "solidAt": [+ "U1.1",+ "U1.3",+ "L1.1",+ "L1.2"+ ],+ "stitchVias": [+ {+ "net": "GND",+ "x": 113.3,+ "y": 92.55,+ "size": 0.6,+ "drill": 0.3+ },+ {+ "net": "GND",+ "x": 113.9,+ "y": 92.75,+ "size": 0.6,+ "drill": 0.3+ },+ {+ "net": "GND",+ "x": 115.55,+ "y": 88.45,+ "size": 0.6,+ "drill": 0.3+ }+ ],+ "fabNote": "3rd party fab, 2-layer, 1.6 mm FR4",+ "fab": {+ "rules": "fab",+ "target": "fab"+ },+ "sourcing": {+ "profile": "fab"+ },+ "molecule": {+ "pin": "medium",+ "gridMm": 2,+ "edgeMarginMm": 2,+ "cornerPinsNet": "GND"+ },+ "planeUnder": [+ {+ "layer": "B.Cu",+ "net": "GND",+ "name": "GND under the input hot loop",+ "polygon": [+ [+ 111.5,+ 82.9+ ],+ [+ 116.4,+ 82.9+ ],+ [+ 116.4,+ 92.6+ ],+ [+ 112.1,+ 92.6+ ],+ [+ 112.1,+ 89.3+ ],+ [+ 111.5,+ 89.3+ ]+ ]+ }+ ],+ "chains": [+ {+ "refs": [+ "R1",+ "R2",+ "C9"+ ],+ "direction": "down"+ }+ ],+ "requireEvidence": [+ "calcs",+ "simulation"+ ],+ "planeUnderNote": "the input hot loop runs from C2/C3/C4 to U1 VIN (pin 3) and GND (pin 1), all on the right of U1; B.Cu under it stays GND so the loop's return images directly beneath it. The polygon covers the three input caps and narrows to U1 pins 1 and 3 below y 89.3, leaving U1's left pins (FB, EN, BOOT) a way down to B.Cu.",+ "voltages": {+ "VIN": 12,+ "VOUT": 5+ },+ "sources": {+ "VOUT": [+ "L1"+ ],+ "SW": [+ "U1"+ ]+ },+ "switching": {+ "SW": {+ "highV": 12,+ "lowV": 0,+ "freqHz": 500000,+ "meanV": 5,+ "riseNs": 8+ }+ },+ "capCurves": "curves",+ "pdn": {+ "VIN": {+ "sourceOhm": 0.05,+ "sourceNh": 1000+ }+ }+}