12 V to 5 V / 1 A Buck Molecule (TPS54202)

@@ -25,7 +25,7 @@ Two minutes of the adom-aiflow run at speed: the pours rework, the current and t | output capacitance | 3 x 22 uF X5R, 36.3 uF effective at 5 V | | loop (ngspice, 12 V, 1 A) | 28.6 kHz crossover, 110 deg phase margin with 68 pF Cff | | output ripple (ngspice, 12 V, 1 A) | 3.2 mV peak to peak |-| load step (TI PSpice model) | about 180 mV (3.6 %) for a 1 A step |+| load step (TI PSpice model) | about 185 mV (3.7 %) for a 1 A step | | efficiency (estimate) | 93 % at 12 V, 1 A | | thermal (Adom Fields, still air) | U1 +44 C at its GND pin, L1 +41 C; 55 C junction-based budget | | board | 28 x 20 mm, 2 layers, 0.5 oz copper, 4 medium machine pins on a 24 x 16 mm grid, 6 contacts, 4 probe pads |

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@@ -50,7 +50,7 @@ Contact positions are in the molecule frame (mm from the centre of MP1), from th | power up | PS1 12.0 V, 0.8 A limit, EN released, no load | VMON reads 2.49 V; TP3 4.98 V; D1 lit | [design](design.md) | | soft start | pull EN low for 100 ms, release; scope TP3 | 95 % in about 4.8 ms, overshoot under 5 mV | [simulation](simulation.md) | | ripple at 1 A | 5 Ohm or 1.0 A electronic load on J4 / J5; TP3 AC-coupled, ground spring to TP4, 20 MHz limit | about 3 to 5 mV pp | ngspice 3.19 mV, TI model 5.0 mV |-| load step | 0.5 to 1 A and 0 to 1 A at 1 A/us; scope TP3 | 80 to 95 mV per 0.5 A step, about 180 mV (3.6 %) for 1 A, settling about 0.2 ms | TI PSpice model |+| load step | 0.5 to 1 A and 0 to 1 A at 1 A/us; scope TP3 | 80 to 95 mV per 0.5 A step, about 185 mV (3.7 %) for 1 A, settling about 0.2 ms | TI PSpice model | | UVLO | no load; sweep PS1 up from 5 V, then down | starts at 8.58 V, stops at 6.87 V | EN divider 1 M / 150 k | | input range | 1 A load; PS1 at 9, 12, 16 V | VOUT 4.98 V at each; PS1 current about 0.6 A at 9 V, 0.45 A at 12 V | 93 % efficiency estimate | | thermal | 1 A, 12 V, still air, 10 min; thermal camera | U1 and L1 about 40 to 45 C above ambient | [thermal and current](thermal-current.md) |

@@ -71,39 +71,55 @@ The switching model agrees with the hand calculation. It gives an inductor rippl  ## 3. TI's PSpice model (validation) -> This comparison was run before the load correction, with both models at the same 1.5 A to 1.0 A to 1.5 A profile, so the two columns still compare like with like and the 0.5 A step conclusion holds. It is being re-run at the corrected 1 A load, alongside LTspice and PSpice runs of the portable model in the Adom SPICE dashboard.+TI publishes a transient model for the TPS54202 (package SLVMBJ5, `TPS54202_TRANS.LIB`). It is Cadence-encrypted, so only PSpice can run it; ngspice cannot. It was run in PSpice for TI with `STEADY_STATE=0` on the same external parts, the same 12 V input and the same 1 A to 0.5 A to 1 A steps, and measured with the same code. The first comparison was run before the load correction, at 1.5 A, on both sides; the figures below are the corrected 1 A runs (2026-09-30). -TI publishes a transient model for the TPS54202 (package SLVMBJ5, `TPS54202_TRANS.LIB`). It is Cadence-encrypted, so only PSpice can run it; ngspice cannot. We ran it in PSpice for TI 23.1 with `STEADY_STATE=0` on the same external parts, the same 12 V input and the same load steps, and measured it with the same metric code as `sim/transient.py`.+![TI encrypted TPS54202 model in PSpice for TI: startup and the load steps](docs/img/ti-pspice-transient.png) -![TI encrypted TPS54202 model in PSpice for TI: startup and the 1 A to 0.5 A to 1 A load steps](docs/img/ti-pspice-transient.png)--| metric (12 V) | fitted ngspice model | TI model |+| metric (12 V, 1 A) | fitted ngspice model | TI model | |---|---|---|-| VOUT mean at 1 A | 4.9787 V | 5.008 V |-| VOUT ripple (peak to peak) at 1 A | 3.17 mV | 5.0 mV (1 mV output quantisation) |-| inductor ripple (peak to peak) | 0.400 A | 0.405 A |-| peak inductor current at startup | 1.723 A | 1.722 A |-| startup overshoot | 2.8 mV | 3.0 mV |-| time to 95 % VOUT | 4.759 ms | 4.838 ms |-| overshoot, 1 A to 0.5 A | 78.4 mV | 91.0 mV |-| undershoot, 0.5 A to 1 A | 77.1 mV | 88.8 mV |-| settling to 1 % after the step up | 204.6 us | 174.1 us |+| VOUT mean at 1 A | 4.9797 V | 5.0088 V |+| VOUT ripple (peak to peak) | 3.19 mV | 5.0 mV (1 mV output quantisation) |+| inductor ripple (peak to peak) | 0.396 A | 0.407 A |+| peak inductor current at startup | 1.226 A | 1.226 A |+| time to 95 % VOUT | 4.757 ms | 4.838 ms |+| overshoot, 1 A to 0.5 A | 79.6 mV | 93.2 mV |+| undershoot, 0.5 A to 1 A | 78.4 mV | 90.7 mV |+| settling to 1 % after the step up | 202.6 us | 171.9 us |  What the comparison shows: -- **Startup, ripple and the inductor current match.** The inductor ripple (0.400 vs 0.405 A) and the startup peak (1.723 vs 1.722 A) agree to within about 1 %.-- **The fitted loop under-predicts the load-step deviation by about 15 %** (78 / 77 mV vs 91 / 89 mV).-- **VOUT is closer to nominal in TI's model.** It settles at 5.008 V, against 4.979 V in the fitted model. TI's model regulates FB to about 0.599 V, while the fitted model used the 0.596 V reference.+- **Startup and the inductor current match.** The startup peak (1.226 A in both) and the inductor ripple (0.40 vs 0.41 A) agree to within about 2 %.+- **The fitted loop under-predicts the load-step deviation by about 15 %** (80 / 78 mV vs 93 / 91 mV), the same gap the 1.5 A runs showed.+- **VOUT is closer to nominal in TI's model** (5.009 V vs 4.980 V): TI's model regulates FB to about 0.599 V, the fitted model uses the 0.596 V reference.++## 4. Three simulators, one answer (Adom SPICE dashboard)++The fitted model was written once as a portable netlist and run in ngspice (in the container), LTspice and PSpice for TI (on a Windows host through Adom Bridge) with the [adom-spice-skillpack](https://wiki.adom.inc/adom/adom-spice-skillpack) dashboard, which measures every engine with the same code and overlays the waveforms. TI's own model is shown as a reference that does not vote.++![Adom SPICE dashboard: ngspice, LTspice and PSpice for TI agree on all 8 measurements; TI's model as a reference](docs/img/spice-dashboard.png)++| measurement (12 V) | ngspice | LTspice | PSpice for TI | spread | TI model (reference) |+|---|---|---|---|---|---|+| VOUT at 1 A | 4.980 V | 4.980 V | 4.980 V | 0.000 | 5.009 V |+| VOUT ripple | 3.27 mV | 2.71 mV | 3.00 mV | 0.56 (limit 1.0) | 5.0 mV |+| inductor ripple | 0.399 A | 0.391 A | 0.390 A | 0.009 | 0.407 A |+| startup peak current | 1.227 A | 1.226 A | 1.226 A | 0.001 | 1.226 A |+| time to 95 % | 4.757 ms | 4.757 ms | 4.757 ms | 0.000 | 4.838 ms |+| overshoot, 1 A to 0.5 A | 79.41 mV | 79.43 mV | 79.28 mV | 0.16 | 93.21 mV |+| undershoot, 0.5 A to 1 A | 78.45 mV | 78.34 mV | 78.77 mV | 0.43 | 90.68 mV |+| settling to 1 % | 200.5 us | 202.4 us | 198.6 us | 3.9 (limit 15) | 171.9 us |++**All three engines agree on all eight measurements**, so the netlist translations are faithful and the 15 % load-step gap is the fitted model against the silicon model, not a simulator difference. LTspice and PSpice run times are not shown: their licences restrict publishing benchmarks.  ## Design conclusion: COUT stays as designed  For this internally compensated part, equation 14 (fo = 3.95 / (VOUT x COUT)) makes fo x COUT a constant. A load step's deviation is roughly dI / (2 pi x fo x COUT), which becomes dI x VOUT / (2 pi x 3.95). COUT cancels out, so the deviation is independent of the output capacitance: about 0.2 V for a full 1 A step. -TI's model agrees. Its 0.5 A steps (91 and 89 mV) scale to about **180 mV for a 1 A step, 3.6 % of 5 V**.+TI's model agrees. At the corrected 1 A load its 0.5 A steps (93 and 91 mV) scale to about **185 mV for a 1 A step, 3.7 % of 5 V**.  - Adding output capacitance would lower the crossover and leave the deviation about the same. - Only a larger Cff would help, and Cff stays at 68 pF to keep the crossover under the datasheet's 40 kHz limit.-- The 3 % step target in `calcs.py` was our own, not part of the brief. 3.6 % is inside the usual +/-5 % window for a 5 V rail.+- The 3 % step target in `calcs.py` was our own, not part of the brief. 3.7 % is inside the usual +/-5 % window for a 5 V rail.  **COUT is unchanged.** The design has not been built yet. When it is, a real 0 to 1 A step on the probing workcell is the next check. 

@@ -84,8 +84,8 @@   {    "name": "load step",    "setup": "electronic load 0 to 1 A and 0.5 to 1 A steps, 1 A/us; scope TP3",-   "check": "0.5 A steps: 80 to 95 mV; full 1 A step about 180 mV (3.6 %), settling about 0.2 ms",-   "source": "TI PSpice model (91 / 89 mV per 0.5 A); the fitted ngspice model says 78 / 77 mV"+   "check": "0.5 A steps: 80 to 95 mV; full 1 A step about 185 mV (3.7 %), settling about 0.2 ms",+   "source": "TI PSpice model (93 / 91 mV per 0.5 A at 1 A); the fitted ngspice model says 78 / 77 mV"   },   {    "name": "UVLO",