                                                                                        DRV8320, DRV8320R, DRV8323, DRV8323R
                                                                                        SLVSDJ3D – FEBRUARY 2017 – REVISED MARCH 2022

                           DRV832x 6 to 60-V Three-Phase Smart Gate Driver
1 Features                                                             3 Description
•   Triple Half-Bridge Gate Driver                                     The DRV832x family of devices is an integrated
    – Drives 3 High-Side and 3 Low-Side N-Channel                      gate driver for three-phase applications. The devices
        MOSFETs (NMOS)                                                 provide three half-bridge gate drivers, each capable
•   Smart Gate Drive Architecture                                      of driving high-side and low-side N-channel power
    – Adjustable Slew Rate Control                                     MOSFETs. The DRV832x generates the correct gate
    – 10-mA to 1-A Peak Source Current                                 drive voltages using an integrated charge pump
    – 20-mA to 2-A Peak Sink Current                                   for the high-side MOSFETs and a linear regulator
•   Integrated Gate Driver Power Supplies                              for the low-side MOSFETs. The Smart Gate Drive
    – Supports 100% PWM Duty Cycle                                     architecture supports peak gate drive currents up to
    – High-Side Charge Pump                                            1A source and 2A. The DRV832x can operate from a
    – Low-Side Linear Regulator                                        single power supply and supports a wide input supply
•   6 to 60-V Operating Voltage Range                                  range of 6 to 60 V for the gate driver and 4 to 60 V for
•   Optional Integrated DC/DC Buck Regulator                           the optional buck regulator.
    – LMR16006X SIMPLE SWITCHER®                                       The 6x, 3x, 1x, and independent input PWM modes
    – 4 to 60-V Operating Voltage Range                                allow for simple interfacing to controller circuits.
    – 0.8 to 60-V, 600-mA Output Capability                            The configuration settings for the gate driver and
•   Optional Integrated Triple Low-Side Current Sense                  device are highly configurable through the SPI
    Amplifiers (CSAs)                                                  or hardware (H/W) interface. The DRV8323 and
    – Adjustable Gain (5, 10, 20, 40 V/V)                              DRV8323R devices integrate three low-side current
    – Bidirectional or Unidirectional Support                          sense amplifiers that allow bidirectional current
•   SPI and Hardware Interface Available                               sensing on all three phases of the drive stage.
•   6x, 3x, 1x, and Independent PWM Modes                              The DRV8320R and DRV8323R devices integrate a
•   Supports 1.8-V, 3.3-V, and 5-V Logic Inputs                        600mA DC/DC buck regulator.
•   Low-Power Sleep Mode (12 µA)                                       A low-power sleep mode is provided to achieve low
•   Linear Voltage Regulator, 3.3 V, 30 mA                             quiescent current draw by shutting down most of
•   Compact QFN Packages and Footprints                                the internal circuitry. Internal protection functions are
•   Efficient System Design With Power Blocks                          provided for undervoltage lockout, charge pump fault,
•   Integrated Protection Features                                     MOSFET overcurrent, MOSFET short circuit, gate
    – VM Undervoltage Lockout (UVLO)                                   driver fault, and overtemperature. Fault conditions are
    – Charge Pump Undervoltage (CPUV)                                  indicated on the nFAULT pin with details through the
    – MOSFET Overcurrent Protection (OCP)                              device registers for SPI device variants.
    – Gate Driver Fault (GDF)
    – Thermal Warning and Shutdown (OTW/OTSD)                                               Device Information
    – Fault Condition Indicator (nFAULT)                                     PART NUMBER          PACKAGE (1)        BODY SIZE (NOM)
                                                                       DRV8320                WQFN (32)             5.00mm × 5.00mm
2 Applications                                                         DRV8320R               VQFN (40)             6.00mm × 6.00mm
•   Brushless-DC (BLDC) Motor Modules and PMSM                         DRV8323                WQFN (40)             6.00mm × 6.00mm
•   Fans, Pumps, and Servo Drives                                      DRV8323R               VQFN (48)             7.00mm × 7.00mm
•   E-Bikes, E-Scooters, and E-Mobility
•   Cordless Garden and Power Tools, Lawnmowers                        (1)    For all available packages, see the orderable addendum at
                                                                              the end of the data sheet.
•   Cordless Vacuum Cleaners
•   Drones, Robotics, and RC Toys
•   Industrial and Logistics Robots




     An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
     intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV8320, DRV8320R, DRV8323, DRV8323R
SLVSDJ3D – FEBRUARY 2017 – REVISED MARCH 2022                                                                                                    www.ti.com

                                                                                     6 to 60 V



                                              PWM                  DRV832x




                                                                                                    N-Channel
                                                                                                    MOSFETs
                                              SPI or H/W          Three-Phase         Gate Drive




                             Controller
                                                                Smart Gate Driver                                       M

                                              nFAULT
                                                                   Protection           Current
                                                                                        Sense
                                             Current Sense     3x Sense Amplifiers
                                                                 (DRV8323 only)
                                              600 mA             Buck Regulator

                                                                      Copyright © 201 7, Texas Instrumen ts Incorpor ate d

                                                             Simplified Schematic




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                                                                                                               DRV8320, DRV8320R, DRV8323, DRV8323R
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                                                                        Table of Contents
1 Features............................................................................1     8.6 Register Maps...........................................................55
2 Applications..................................................................... 1     9 Application and Implementation.................................. 63
3 Description.......................................................................1       9.1 Application Information............................................. 63
4 Revision History.............................................................. 3          9.2 Typical Application.................................................... 63
5 Device Comparison Table...............................................5                 10 Power Supply Recommendations..............................73
6 Pin Configuration and Functions...................................5                       10.1 Power Supply Consideration in Generator Mode....73
7 Specifications................................................................ 12         10.2 Bulk Capacitance Sizing......................................... 74
  7.1 Absolute Maximum Ratings...................................... 12                   11 Layout........................................................................... 75
  7.2 ESD Ratings............................................................. 13           11.1 Layout Guidelines................................................... 75
  7.3 Recommended Operating Conditions.......................13                             11.2 Layout Example...................................................... 77
  7.4 Thermal Information..................................................13             12 Device and Documentation Support..........................78
  7.5 Electrical Characteristics...........................................14               12.1 Device Support....................................................... 78
  7.6 SPI Timing Requirements......................................... 19                   12.2 Documentation Support.......................................... 78
  7.7 Typical Characteristics.............................................. 20              12.3 Receiving Notification of Documentation Updates..78
8 Detailed Description......................................................22              12.4 Support Resources................................................. 78
  8.1 Overview................................................................... 22        12.5 Trademarks............................................................. 79
  8.2 Functional Block Diagram......................................... 23                  12.6 Electrostatic Discharge Caution..............................79
  8.3 Feature Description...................................................31              12.7 Glossary..................................................................79
  8.4 Device Functional Modes..........................................51                 13 Mechanical, Packaging, and Orderable
  8.5 Programming............................................................ 53            Information.................................................................... 79



4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (August 2018) to Revision D (March 2022)                                      Page
• Added information in the Sleep Mode section on the behavior of GHx and GLx w hen Enable is pulled low.. 51



Changes from Revision B (December 2017) to Revision C (August 2018)                                                                                   Page
• Changed the Applications ..................................................................................................................................1
• Updated input labels for the INLx and INHx signals in the Layout Example imags.......................................... 77
• Added the DRV835x device options to the image in the Device Nomenclature section...................................78



Changes from Revision A (April 2017) to Revision B (December 2017)                                                                                            Page
• Changed the low-power sleep mode supply current from the maximum value (20 µA) to the typical value (12
  µA) in the Features ............................................................................................................................................1
• Changed the Applications ..................................................................................................................................1
• Changed the GAIN value from 45kΩ to 47kΩ in the test condition of the amplifier gain for the H/W device in
  the Electrical Characteristics table....................................................................................................................14
• Deleted tEN_nSCS from the SPI Secondary Mode Timing Diagram ...................................................................19
• Added a note to the Synchronous 1x PWM Mode to define !PWM ................................................................. 32
• Updated the Auto Offset Calibration section.....................................................................................................45
• Updated the VDS Latched Shutdown and VDS Automatic Retry sections......................................................... 49
• Updated the Sleep Mode section......................................................................................................................51
• Changed the address listed in the title for the Gate Drive LS Register section to the correct register
  address, 0x04................................................................................................................................................... 60
• Changed the maximum Qg value for both trapezoidal and sinusoidal commutation the VVM = 8 V example of
  the Detailed Design Procedure ........................................................................................................................65
• Changed IDRIVEP and IDRIVEN equations in the IDRIVE Configuration section..................................................65



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                                               Product Folder Links: DRV8320 DRV8320R DRV8323 DRV8323R
DRV8320, DRV8320R, DRV8323, DRV8323R
SLVSDJ3D – FEBRUARY 2017 – REVISED MARCH 2022                                                                                 www.ti.com

Changes from Revision * (February 2017) to Revision A (April 2017)                                                             Page
• Changed the test condition for the IBIAS parameter in the Electrical Characteristics table............................... 14
• Changed the GHx values in the 3x PWM Mode Truth Table ........................................................................... 32
• Changed the calibration description and added auto calibration feature description ...................................... 45




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                                   Product Folder Links: DRV8320 DRV8320R DRV8323 DRV8323R
                                                                                                                                              DRV8320, DRV8320R, DRV8323, DRV8323R
www.ti.com                                                                                                                                    SLVSDJ3D – FEBRUARY 2017 – REVISED MARCH 2022


5 Device Comparison Table
                                                                                                         CURRENT SENSE
               DEVICE                                     VARIANT(1)                                                                     BUCK REGULATOR(1)                                        INTERFACE(1)
                                                                                                           AMPLIFIERS
                                                            DRV8320H                                                                                                                                     Hardware
               DRV8320                                                                                                                                     None
                                                            DRV8320S                                                                                                                                          SPI
                                                                                                                   0
                                                          DRV8320RH                                                                                                                                      Hardware
           DRV8320R                                                                                                                                 600 mA
                                                          DRV8320RS                                                                                                                                           SPI
                                                            DRV8323H                                                                                                                                     Hardware
               DRV8323                                                                                                                                     None
                                                            DRV8323S                                                                                                                                          SPI
                                                                                                                   3
                                                          DRV8323RH                                                                                                                                      Hardware
           DRV8323R                                                                                                                                 600 mA
                                                          DRV8323RS                                                                                                                                           SPI

(1)     For more information on the device name and device options, see Section 12.1.1. For additional details, see the Architecture for
        Brushless-DC Gate Drive Systems application report.

6 Pin Configuration and Functions
                                   PGND




                                                                                                                                                    PGND
                                                   INHC




                                                                                                                                                                    INHC
                                                                     INHB




                                                                                       INHA




                                                                                                                                                                                    INHB




                                                                                                                                                                                                  INHA
                                            INLC




                                                                                                                                                             INLC
                                                            INLB




                                                                             INLA




                                                                                                                                                                             INLB




                                                                                                                                                                                           INLA
                           CPL




                                                                                                                                              CPL
                           32

                                   31

                                            30

                                                   29

                                                            28

                                                                     27

                                                                             26

                                                                                       25




                                                                                                                                              32

                                                                                                                                                    31

                                                                                                                                                             30

                                                                                                                                                                    29

                                                                                                                                                                             28

                                                                                                                                                                                    27

                                                                                                                                                                                           26

                                                                                                                                                                                                  25
        CPH         1                                                                         24          DVDD            CPH           1                                                                24           DVDD

        VCP         2                                                                         23          AGND             VCP          2                                                                23           AGND

         VM         3                                                                         22          ENABLE            VM          3                                                                22           ENABLE

      VDRAIN        4                                                                         21          NC           VDRAIN           4                                                                21           nSCS
                                                   Thermal                                                                                                          Thermal
        GHA         5                                 Pad                                     20          VDS             GHA           5                              Pad                               20           SCLK

        SHA         6                                                                         19          IDRIVE           SHA          6                                                                19           SDI

        GLA         7                                                                         18          MODE             GLA          7                                                                18           SDO

        SLA         8                                                                         17          nFAULT           SLA          8                                                                17           nFAULT
                                   10

                                            11

                                                   12

                                                            13

                                                                     14

                                                                             15

                                                                                       16




                                                                                                                                                    10

                                                                                                                                                             11

                                                                                                                                                                    12

                                                                                                                                                                             13

                                                                                                                                                                                    14

                                                                                                                                                                                           15

                                                                                                                                                                                                  16
                           9




                                                                                                                                              9
                           SLB

                                   GLB

                                            SHB

                                                   GHB

                                                            GHC

                                                                     SHC

                                                                             GLC

                                                                                       SLC




                                                                                                                                              SLB

                                                                                                                                                    GLB

                                                                                                                                                             SHB

                                                                                                                                                                    GHB

                                                                                                                                                                             GHC

                                                                                                                                                                                    SHC

                                                                                                                                                                                           GLC

                                                                                                                                                                                                  SLC



                                                                                                   Not to scale                                                                                                Not to scale

  Figure 6-1. DRV8320H RTV Package 32-Pin WQFN                                                                         Figure 6-2. DRV8320S RTV Package 32-Pin WQFN
        With Exposed Thermal Pad Top View                                                                                    With Exposed Thermal Pad Top View

                                                            Table 6-1. Pin Functions—32-Pin DRV8320 Devices
                     PIN
                                 NO.                               TYPE(1)                                                                  DESCRIPTION
 NAME
                 DRV8320H                 DRV8320S
 AGND               23                       23                     PWR             Device analog ground. Connect to system ground. AGND must be connected to PGND externally.
 CPH                1                         1                     PWR             Charge pump switching node. Connect an X5R or X7R, 47nF, VM-rated ceramic capacitor between the CPH and CPL pins.
 CPL                32                       32                     PWR             For example, in a 24V system the capacitor should be rated 50V (2x margin).

                                                                                    3.3V internal regulator output. Connect an X5R or X7R, 1µF, 6.3V ceramic capacitor between the DVDD and AGND pins.
 DVDD               24                       24                     PWR
                                                                                    This regulator can source up to 30 mA externally.
                                                                                    Gate driver enable. When this pin is logic low the device goes to a low-power sleep mode. An 8 to 40µs pulse can be used to
 ENABLE             22                       22                       I
                                                                                    reset fault conditions without entering sleep mode.
 GHA                5                         5                      O              High-side gate driver output. Connect to the gate of the high-side power MOSFET.
 GHB                12                       12                      O              High-side gate driver output. Connect to the gate of the high-side power MOSFET.
 GHC                13                       13                      O              High-side gate driver output. Connect to the gate of the high-side power MOSFET.
 GLA                7                         7                      O              Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
 GLB                10                       10                      O              Low-side gate driver output. Connect to the gate of the low-side power MOSFET.



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DRV8320, DRV8320R, DRV8323, DRV8323R
SLVSDJ3D – FEBRUARY 2017 – REVISED MARCH 2022                                                                                                                             www.ti.com

                                    Table 6-1. Pin Functions—32-Pin DRV8320 Devices (continued)
                     PIN
                            NO.              TYPE(1)                                                             DESCRIPTION
    NAME
                 DRV8320H         DRV8320S
    GLC             15               15        O       Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
    IDRIVE          19               —          I      Gate drive output current setting. This pin is a 7 level input pin set by an external resistor.
    INHA            25               25         I      High-side gate driver control input. This pin controls the output of the high-side gate driver when using 6x PWM mode.
    INHB            27               27         I      High-side gate driver control input. This pin controls the output of the high-side gate driver when using 6x PWM mode.
    INHC            29               29         I      High-side gate driver control input. This pin controls the output of the high-side gate driver when using 6x PWM mode.
    INLA            26               26         I      Low-side gate driver control input. This pin controls the output of the low-side gate driver when using 6x PWM mode.
    INLB            28               28         I      Low-side gate driver control input. This pin controls the output of the low-side gate driver when using 6x PWM mode.
    INLC            30               30         I      Low-side gate driver control input. This pin controls the output of the low-side gate driver when using 6x PWM mode.
    MODE            18               —          I      PWM input mode setting. This pin is a 4 level input pin set by an external resistor.
    NC              21               —         NC      No internal connection. This pin can be left floating or connected to system ground.
    nFAULT          17               17        OD      Fault indicator output. This open drain pin pulls logic low during a fault condition and requires an external pullup resistor.
    nSCS            —                21         I      Serial chip select. A logic low on this pin enables serial interface communication.
                                                       Device power ground. Also used as the gate drive sink path for the low side MOSFETs. Connect to system ground. PGND
    PGND            31               31       PWR
                                                       must be connected to AGND externally.
    SCLK            —                20         I      Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin.
    SDI             —                19         I      Serial data input. Data is captured on the falling edge of the SCLK pin.
                                                       Serial data output. Data is shifted out on the rising edge of the SCLK pin. This open drain pin requires an external pullup
    SDO             —                18        OD
                                                       resistor.
                                                       High-side source pin. Connect to the high-side power MOSFET source. This pin is an input for the VDS monitor and the
    SHA             6                6         I/O
                                                       output for the high-side gate driver sink.
                                                       High-side source pin. Connect to the high-side power MOSFET source. This pin is an input for the VDS monitor and the
    SHB             11               11        I/O
                                                       output for the high-side gate driver sink.
                                                       High-side source pin. Connect to the high-side power MOSFET source. This pin is an input for the VDS monitor and the
    SHC             14               14        I/O
                                                       output for the high-side gate driver sink.
    SLA             8                8          I      Low-side source input. Connect to the low-side power MOSFET source. This pin is an input for the VDS monitor.
    SLB             9                9          I      Low-side source input. Connect to the low-side power MOSFET source. This pin is an input for the VDS monitor.
    SLC             16               16         I      Low-side source input. Connect to the low-side power MOSFET source. This pin is an input for the VDS monitor.
    VCP             2                2        PWR      Charge pump output. Connect an X5R or X7R, 1µF, 25V ceramic capacitor between the VCP and VM pins.
                                                       High-side MOSFET drain input. Connect to the common point of the high-side MOSFET drains. This pin is an input for the
    VDRAIN          4                4          I
                                                       VDS monitor.
    VDS             20               —          I      VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor.
                                                       Gate driver power supply input. Connect to the motor power supply and VDRAIN. Connect an X5R or X7R, 0.1µF, VM-rated
    VM              3                3        PWR
                                                       ceramic and greater then or equal to 10-uF local capacitance between the VM and PGND pins.
    Thermal
                   PAD              PAD       PWR      Must be connected to ground
    Pad


(1)        PWR = power, I = input, O = output, NC = no connection, OD = open-drain output




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                                 nSHDN




                                                                                                                                                       nSHDN
                                                                     BGND




                                                                                                                                                                                         BGND
                                                                                    INHC




                                                                                                                                                                                                       INHC
                                                                            INLC




                                                                                                                                                                                                INLC
                                                                                           INLB




                                                                                                                                                                                                              INLB
                                         VIN




                                                                                                                                                               VIN
                                                     SW




                                                                                                                                                                           SW
                                               NC




                                                                                                                                                                     NC
                                                             CB




                                                                                                                                                                                   CB
                           FB




                                                                                                                                                FB
                           40

                                 39

                                         38

                                               37

                                                     36

                                                             35

                                                                     34

                                                                            33

                                                                                    32

                                                                                           31




                                                                                                                                                40

                                                                                                                                                       39

                                                                                                                                                               38

                                                                                                                                                                     37

                                                                                                                                                                           36

                                                                                                                                                                                   35

                                                                                                                                                                                         34

                                                                                                                                                                                                33

                                                                                                                                                                                                       32

                                                                                                                                                                                                              31
        PGND      1                                                                                 30          INHB       PGND           1                                                                            30          INHB

         CPL      2                                                                                 29          INLA         CPL          2                                                                            29          INLA

         CPH      3                                                                                 28          INHA         CPH          3                                                                            28          INHA

         VCP      4                                                                                 27          DVDD         VCP          4                                                                            27          DVDD

          VM      5                                                                                 26          AGND          VM          5                                                                            26          AGND
                                                     Thermal                                                                                                               Thermal
      VDRAIN      6                                    Pad                                          25          ENABLE    VDRAIN          6                                  Pad                                       25          ENABLE

         GHA      7                                                                                 24          NC           GHA          7                                                                            24          nSCS

         SHA      8                                                                                 23          VDS          SHA          8                                                                            23          SCLK

         GLA      9                                                                                 22          IDRIVE       GLA          9                                                                            22          SDI

         SLA      10                                                                                21          MODE         SLA          10                                                                           21          SDO
                           11

                                 12

                                         13

                                               14

                                                     15

                                                             16

                                                                     17

                                                                            18

                                                                                    19

                                                                                           20




                                                                                                                                                11

                                                                                                                                                       12

                                                                                                                                                               13

                                                                                                                                                                     14

                                                                                                                                                                           15

                                                                                                                                                                                   16

                                                                                                                                                                                         17

                                                                                                                                                                                                18

                                                                                                                                                                                                       19

                                                                                                                                                                                                              20
                           SLB

                                 GLB

                                         SHB

                                               GHB

                                                     GHC

                                                             SHC

                                                                     GLC

                                                                            SLC

                                                                                    GND

                                                                                           nFAULT




                                                                                                                                                SLB

                                                                                                                                                       GLB

                                                                                                                                                               SHB

                                                                                                                                                                     GHB

                                                                                                                                                                           GHC

                                                                                                                                                                                   SHC

                                                                                                                                                                                         GLC

                                                                                                                                                                                                SLC

                                                                                                                                                                                                       GND

                                                                                                                                                                                                              nFAULT
                                                                                                         Not to scale                                                                                                       Not to scale


 Figure 6-3. DRV8320RH RHA Package 40-Pin VQFN Figure 6-4. DRV8320RS RHA Package 40-Pin VQFN
        With Exposed Thermal Pad Top View             With Exposed Thermal Pad Top View

                                                           Table 6-2. Pin Functions—40-Pin DRV8320R Devices
                          PIN
                                 NO.                               TYPE(1)                                                                     DESCRIPTION
 NAME
               DRV8320RH                 DRV8320RS
 AGND             26                           26                   PWR            Device analog ground. Connect to system ground. AGND must be connected to BGND and PGND externally.
 BGND             34                           34                   PWR            Buck regulator ground. Connect to system ground. BGND must be connected to AGND and PGND externally.
 CB               35                           35                   PWR            Buck regulator bootstrap input. Connect an X5R or X7R, 0.1µF, 16V, capacitor between the CB and SW pins.
 CPH                  3                        3                    PWR            Charge pump switching node. Connect an X5R or X7R, 47nF, VM-rated ceramic capacitor between the CPH and CPL pins.
 CPL                  2                        2                    PWR            For example, in a 24V system the capacitor should be rated 50V (2x margin).

                                                                                   3.3V internal regulator output. Connect an X5R or X7R, 1µF, 6.3V ceramic capacitor between the DVDD and AGND pins.
 DVDD             27                           27                   PWR
                                                                                   This regulator can source up to 30mA externally.
                                                                                   Gate driver enable. When this pin is logic low the device goes to a low-power sleep mode. An 8 to 40µs low pulse can be
 ENABLE           25                           25                      I
                                                                                   used to reset fault conditions without entering sleep mode.
 FB               40                           40                      I           Buck feedback input. A resistor divider from the buck post inductor output to this pin sets the buck output voltage.
 GHA                  7                        7                      O            High-side gate driver output. Connect to the gate of the high-side power MOSFET.
 GHB              14                           14                     O            High-side gate driver output. Connect to the gate of the high-side power MOSFET.
 GHC              15                           15                     O            High-side gate driver output. Connect to the gate of the high-side power MOSFET.
 GLA                  9                        9                      O            Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
 GLB              12                           12                     O            Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
 GLC              17                           17                     O            Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
 GND              19                           19                   PWR            Device ground. Connect to system ground.
 IDRIVE           22                           —                       I           Gate drive output current setting. This pin is a 7 level input pin set by an external resistor.
 INHA             28                           28                      I           High-side gate driver control input. This pin controls the output of the high-side gate driver when using 6x PWM mode.
 INHB             30                           30                      I           High-side gate driver control input. This pin controls the output of the high-side gate driver when using 6x PWM mode.
 INHC             32                           32                      I           High-side gate driver control input. This pin controls the output of the high-side gate driver when using 6x PWM mode.
 INLA             29                           29                      I           Low-side gate driver control input. This pin controls the output of the low-side gate driver when using 6x PWM mode.
 INLB             31                           31                      I           Low-side gate driver control input. This pin controls the output of the low-side gate driver when using 6x PWM mode.
 INLC             33                           33                      I           Low-side gate driver control input. This pin controls the output of the low-side gate driver when using 6x PWM mode.
 MODE             21                           —                       I           PWM input mode setting. This pin is a 4 level input pin set by an external resistor.
 NC               24                           —                     NC            No internal connection. This pin can be left floating or connected to system ground.
 NC               37                           37                    NC            No internal connection. This pin can be left floating or connected to system ground.
 nFAULT           20                           20                    OD            Fault indicator output. This open drain pin pulls logic low during a fault condition and requires an external pullup resistor.
 nSCS             —                            24                      I           Serial chip select. A logic low on this pin enables serial interface communication.
                                                                                   Buck shutdown input. Enable and disable input (high voltage tolerant). Internal pullup current source. Pull lower than 1.25V to
 nSHDN            39                           39                      I
                                                                                   disable. Float to enable. Establish input undervoltage lockout with two resistor divider.


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                                                               Product Folder Links: DRV8320 DRV8320R DRV8323 DRV8323R
DRV8320, DRV8320R, DRV8323, DRV8323R
SLVSDJ3D – FEBRUARY 2017 – REVISED MARCH 2022                                                                                                                                                                                          www.ti.com

                                                   Table 6-2. Pin Functions—40-Pin DRV8320R Devices (continued)
                             PIN
                                     NO.                                   TYPE(1)                                                                     DESCRIPTION
    NAME
                  DRV8320RH                 DRV8320RS
                                                                                           Device power ground. Also used as the gate drive sink path for the low side MOSFETs. Connect to system ground. PGND
    PGND                 1                          1                       PWR
                                                                                           mut be connected to AGND and BGND externally.
    SCLK             —                             23                          I           Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin.
    SDI              —                             22                          I           Serial data input. Data is captured on the falling edge of the SCLK pin.
                                                                                           Serial data output. Data is shifted out on the rising edge of the SCLK pin. This open drain pin requires an external pullup
    SDO              —                             21                        OD
                                                                                           resistor.

                                                                                           High-side source pin. Connect to the high-side power MOSFET source. This pin is an input for the VDS monitor and the
    SHA                  8                          8                        I/O
                                                                                           output for the high-side gate driver sink.

                                                                                           High-side source pin. Connect to the high-side power MOSFET source. This pin is an input for the VDS monitor and the
    SHB              13                            13                        I/O
                                                                                           output for the high-side gate driver sink.
                                                                                           High-side source pin. Connect to the high-side power MOSFET source. This pin is an input for the VDS monitor and the
    SHC              16                            16                        I/O
                                                                                           output for the high-side gate driver sink.
    SLA              10                            10                          I           Low-side source input. Connect to the low-side power MOSFET source. This pin is an input for the VDS monitor.
    SLB              11                            11                          I           Low-side source input. Connect to the low-side power MOSFET source. This pin is an input for the VDS monitor.
    SLC              18                            18                          I           Low-side source input. Connect to the low-side power MOSFET source. This pin is an input for the VDS monitor.
    SW               36                            36                         O            Buck switch node. Connect this pin to an inductor, diode, and the CB bootstrap capacitor.
    VCP                  4                          4                       PWR            Charge pump output. Connect an X5R or X7R, 1µF, 25V ceramic capacitor between the VCP and VM pins.
                                                                                           High-side MOSFET drain input. Connect to the common point of the high-side MOSFET drains. This pin is an input for the
    VDRAIN               6                          6                          I
                                                                                           VDS monitor.
    VDS              23                            —                           I           VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor.
    VIN              38                            38                       PWR            Buck regulator power supply input. Place an X5R or X7R, VM-rated ceramic capacitor between the VIN and BGND pins.
                                                                                           Gate driver power supply input. Connect to the motor power supply and VDRAIN. Connect an X5R or X7R, 0.1µF, VM-rated
    VM                   5                          5                       PWR
                                                                                           ceramic and greater then or equal to 10-uF local capacitance between the VM and PGND pins.
    Thermal
                    PAD                            PAD                      PWR            Must be connected to ground
    Pad


(1)         PWR = power, I = input, O = output, NC = no connection, OD = open-drain output
                              PGND




                                                                                            AGND




                                                                                                                                                        PGND




                                                                                                                                                                                                                   AGND
                                                                                    DVDD




                                                                                                                                                                                                            DVDD
                                            INHC




                                                                                                                                                                      INHC
                                                           INHB




                                                                             INHA




                                                                                                                                                                                     INHB




                                                                                                                                                                                                     INHA
                                     INLC




                                                                                                                                                               INLC
                                                    INLB




                                                                    INLA




                                                                                                                                                                              INLB




                                                                                                                                                                                              INLA
                                                                                                   CAL




                                                                                                                                                                                                                          CAL
                              40

                                     39

                                            38

                                                    37

                                                           36

                                                                    35

                                                                             34

                                                                                    33

                                                                                            32

                                                                                                   31




                                                                                                                                                        40

                                                                                                                                                               39

                                                                                                                                                                      38

                                                                                                                                                                              37

                                                                                                                                                                                     36

                                                                                                                                                                                              35

                                                                                                                                                                                                     34

                                                                                                                                                                                                            33

                                                                                                                                                                                                                   32

                                                                                                                                                                                                                          31
           CPL       1                                                                                   30          ENABLE             CPL       1                                                                             30          ENABLE

           CPH       2                                                                                   29          GAIN               CPH       2                                                                             29          nSCS

           VCP       3                                                                                   28          VDS                VCP       3                                                                             28          SCLK

            VM       4                                                                                   27          IDRIVE             VM        4                                                                             27          SDI

         VDRAIN      5                                                                                   26          MODE         VDRAIN          5                                                                             26          SDO
                                                           Thermal                                                                                                                   Thermal
           GHA       6                                        Pad                                        25          nFAULT          GHA          6                                     Pad                                     25          nFAULT

           SHA       7                                                                                   24          VREF               SHA       7                                                                             24          VREF

           GLA       8                                                                                   23          SOA                GLA       8                                                                             23          SOA

           SPA       9                                                                                   22          SOB                SPA       9                                                                             22          SOB

           SNA       10                                                                                  21          SOC                SNA       10                                                                            21          SOC
                              11

                                     12

                                            13

                                                    14

                                                           15

                                                                    16

                                                                             17

                                                                                    18

                                                                                            19

                                                                                                   20




                                                                                                                                                        11

                                                                                                                                                               12

                                                                                                                                                                      13

                                                                                                                                                                              14

                                                                                                                                                                                     15

                                                                                                                                                                                              16

                                                                                                                                                                                                     17

                                                                                                                                                                                                            18

                                                                                                                                                                                                                   19

                                                                                                                                                                                                                          20
                              SNB

                                     SPB

                                            GLB

                                                    SHB

                                                           GHB

                                                                    GHC

                                                                             SHC

                                                                                    GLC

                                                                                            SPC

                                                                                                   SNC




                                                                                                                                                        SNB

                                                                                                                                                               SPB

                                                                                                                                                                      GLB

                                                                                                                                                                              SHB

                                                                                                                                                                                     GHB

                                                                                                                                                                                              GHC

                                                                                                                                                                                                     SHC

                                                                                                                                                                                                            GLC

                                                                                                                                                                                                                   SPC

                                                                                                                                                                                                                          SNC




                                                                                                              Not to scale                                                                                                           Not to scale

     Figure 6-5. DRV8323H RTA Package 40-Pin WQFN                                                                               Figure 6-6. DRV8323S RTA Package 40-Pin WQFN
           With Exposed Thermal Pad Top View                                                                                          With Exposed Thermal Pad Top View

                                                                    Table 6-3. Pin Functions—40-Pin DRV8323 Devices
                             PIN
                                     NO.                                   TYPE(1)                                                                     DESCRIPTION
    NAME
                  DRV8323H                  DRV8323S
    AGND             32                            32                       PWR            Device analog ground. Connect to system ground. AGND must be connected to PGND externally.


8           Submit Document Feedback                                                                                                                                         Copyright © 2026 Texas Instruments Incorporated

                                                                       Product Folder Links: DRV8320 DRV8320R DRV8323 DRV8323R
                                                                                                                    DRV8320, DRV8320R, DRV8323, DRV8323R
www.ti.com                                                                                                           SLVSDJ3D – FEBRUARY 2017 – REVISED MARCH 2022

                                    Table 6-3. Pin Functions—40-Pin DRV8323 Devices (continued)
                     PIN
                           NO.              TYPE(1)                                                              DESCRIPTION
 NAME
            DRV8323H             DRV8323S
 CAL            31                  31         I      Amplifier calibration input. Set logic high to internally short amplifier inputs and perform auto offset calibration.
 CPH            2                   2        PWR      Charge pump switching node. Connect an X5R or X7R, 47nF, VM-rated ceramic capacitor between the CPH and CPL pins.
 CPL            1                   1        PWR      For example, in a 24V system the capacitor should be rated 50V (2x margin).

                                                      3.3V internal regulator output. Connect an X5R or X7R, 1µF, 6.3V ceramic capacitor between the DVDD and AGND pins. This
 DVDD           33                  33       PWR
                                                      regulator can source up to 30mA externally.
                                                      Gate driver enable. When this pin is logic low the device goes to a low-power sleep mode. An 8 to 40µs low pulse can be
 ENABLE         30                  30         I
                                                      used to reset fault conditions without entering sleep mode.
 GAIN           29                  —          I      Amplifier gain setting. The pin is a 4 level input pin set by an external resistor.
 GHA            6                   6         O       High-side gate driver output. Connect to the gate of the high-side power MOSFET.
 GHB            15                  15        O       High-side gate driver output. Connect to the gate of the high-side power MOSFET.
 GHC            16                  16        O       High-side gate driver output. Connect to the gate of the high-side power MOSFET.
 GLA            8                   8         O       Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
 GLB            13                  13        O       Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
 GLC            18                  18        O       Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
 IDRIVE         27                  —          I      Gate drive output current setting. This pin is a 7 level input pin set by an external resistor.
 INHA           34                  34         I      High-side gate driver control input. This pin controls the output of the high-side gate driver when using 6x PWM mode.
 INHB           36                  36         I      High-side gate driver control input. This pin controls the output of the high-side gate driver when using 6x PWM mode.
 INHC           38                  38         I      High-side gate driver control input. This pin controls the output of the high-side gate driver when using 6x PWM mode.
 INLA           35                  35         I      Low-side gate driver control input. This pin controls the output of the low-side gate driver when using 6x PWM mode.
 INLB           37                  37         I      Low-side gate driver control input. This pin controls the output of the low-side gate driver when using 6x PWM mode.
 INLC           39                  39         I      Low-side gate driver control input. This pin controls the output of the low-side gate driver when using 6x PWM mode.
 MODE           26                  —          I      PWM input mode setting. This pin is a 4 level input pin set by an external resistor.
 nFAULT         25                  25        OD      Fault indicator output. This open drain pin pulls logic low during a fault condition and requires an external pullup resistor.
 nSCS           —                   29         I      Serial chip select. A logic low on this pin enables serial interface communication.
                                                      Device power ground. Also used as the gate drive sink path for the low side MOSFETs. Connect to system ground. PGND
 PGND           40                  40       PWR
                                                      must be connected to AGND externally.
 SCLK           —                   28         I      Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin.
 SDI            —                   27         I      Serial data input. Data is captured on the falling edge of the SCLK pin.
                                                      Serial data output. Data is shifted out on the rising edge of the SCLK pin. This open drain pin requires an external pullup
 SDO            —                   26        OD
                                                      resistor.

                                                      High-side source pin. Connect to the high-side power MOSFET source. This pin is an input for the VDS monitor and the
 SHA            7                   7         I/O
                                                      output for the high-side gate driver sink.

                                                      High-side source pin. Connect to the high-side power MOSFET source. This pin is an input for the VDS monitor and the
 SHB            14                  14        I/O
                                                      output for the high-side gate driver sink.
                                                      High-side source pin. Connect to the high-side power MOSFET source. This pin is an input for the VDS monitor and the
 SHC            17                  17        I/O
                                                      output for the high-side gate driver sink.
 SNA            10                  10         I      Current sense amplifier input. Connect to the low-side of the current shunt resistor. If CSA is not used tie to PGND.
 SNB            11                  11         I      Current sense amplifier input. Connect to the low-side of the current shunt resistor. If CSA is not used tie to PGND.
 SNC            20                  20         I      Current sense amplifier input. Connect to the low-side of the current shunt resistor. If CSA is not used tie to PGND.
 SOA            23                  23        O       Current sense amplifier output. If CSA is not used leave this pin disconnected.
 SOB            22                  22        O       Current sense amplifier output. If CSA is not used leave this pin disconnected.
 SOC            21                  21        O       Current sense amplifier output. If CSA is not used leave this pin disconnected.
                                                      Low-side current shunt amplifier input. Also VDS monitor negative input for low side MOSFET. Connect to the low-side power
 SPA            9                   9          I
                                                      MOSFET source and high-side of the current shunt resistor. If CSA is not used tie to SNA.
                                                      Low-side current shunt amplifier input. Also VDS monitor negative input for low side MOSFET. Connect to the low-side power
 SPB            12                  12         I
                                                      MOSFET source and high-side of the current shunt resistor. If CSA is not used tie to SNB.
                                                      Low-side current shunt amplifier input. Also VDS monitor negative input for low side MOSFET. Connect to the low-side power
 SPC            19                  19         I
                                                      MOSFET source and high-side of the current shunt resistor. If CSA is not used tie to SNC.
 VCP            3                   3        PWR      Charge pump output. Connect an X5R or X7R, 1µF, 25V ceramic capacitor between the VCP and VM pins.
                                                      High-side MOSFET drain input. Connect to the common point of the high-side MOSFET drains. This pin is an input for the
 VDRAIN         5                   5          I
                                                      VDS monitor.
 VDS            28                  —          I      VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor.
                                                      Gate driver power supply input. Connect to the motor power supply and VDRAIN. Connect an X5R or X7R, 0.1µF, VM-rated
 VM             4                   4        PWR
                                                      ceramic and greater then or equal to 10uF local capacitance between the VM and PGND pins.
                                                      Current sense amplifier power supply input and reference. Connect an X5R or X7R, 0.1µF, 6.3V ceramic capacitor between
 VREF           24                  24       PWR
                                                      the VREF and AGND pins.




Copyright © 2026 Texas Instruments Incorporated                                                                                             Submit Document Feedback                   9
                                            Product Folder Links: DRV8320 DRV8320R DRV8323 DRV8323R
DRV8320, DRV8320R, DRV8323, DRV8323R
SLVSDJ3D – FEBRUARY 2017 – REVISED MARCH 2022                                                                                                                                                                                                          www.ti.com

                                                        Table 6-3. Pin Functions—40-Pin DRV8323 Devices (continued)
                          PIN
                                        NO.                                       TYPE(1)                                                                     DESCRIPTION
 NAME
               DRV8323H                         DRV8323S
 Thermal
                 PAD                                    PAD                        PWR            Must be connected to ground
 Pad


(1)      PWR = power, I = input, O = output, NC = no connection, OD = open-drain output
                          nSHDN




                                                                                                                                                             nSHDN
                                                                  BGND




                                                                                                                                                                                               BGND
                                                                                    INHC




                                                                                                                                                                                                               INHC
                                                                                                  INHB




                                                                                                                INHA




                                                                                                                                                                                                                             INHB




                                                                                                                                                                                                                                           INHA
                                                                           INLC




                                                                                                                                                                                                        INLC
                                                                                           INLB




                                                                                                         INLA




                                                                                                                                                                                                                      INLB




                                                                                                                                                                                                                                    INLA
                                  VIN




                                                                                                                                                                     VIN
                                                  SW




                                                                                                                                                                                 SW
                                          NC




                                                                                                                                                                           NC
                                                            CB




                                                                                                                                                                                         CB
                          48

                                  47

                                          46

                                                  45

                                                            44

                                                                  43

                                                                           42

                                                                                    41

                                                                                           40

                                                                                                  39

                                                                                                         38

                                                                                                                37




                                                                                                                                                             48

                                                                                                                                                                     47

                                                                                                                                                                           46

                                                                                                                                                                                 45

                                                                                                                                                                                         44

                                                                                                                                                                                               43

                                                                                                                                                                                                        42

                                                                                                                                                                                                               41

                                                                                                                                                                                                                      40

                                                                                                                                                                                                                             39

                                                                                                                                                                                                                                    38

                                                                                                                                                                                                                                           37
         FB      1                                                                                                     36          DVDD        FB       1                                                                                         36          DVDD

       PGND      2                                                                                                     35          AGND      PGND       2                                                                                         35          AGND

        CPL      3                                                                                                     34          CAL        CPL       3                                                                                         34          CAL

        CPH      4                                                                                                     33          ENABLE     CPH       4                                                                                         33          ENABLE

        VCP      5                                                                                                     32          GAIN       VCP       5                                                                                         32          nSCS

         VM      6                                                                                                     31          VDS         VM       6                                                                                         31          SCLK
                                                                  Thermal                                                                                                                      Thermal
      VDRAIN     7                                                   Pad                                               30          IDRIVE   VDRAIN      7                                         Pad                                             30          SDI

        GHA      8                                                                                                     29          MODE       GHA       8                                                                                         29          SDO

        SHA      9                                                                                                     28          nFAULT     SHA       9                                                                                         28          nFAULT

        GLA      10                                                                                                    27          DGND       GLA       10                                                                                        27          DGND

        SPA      11                                                                                                    26          VREF       SPA       11                                                                                        26          VREF

        SNA      12                                                                                                    25          SOA        SNA       12                                                                                        25          SOA
                          13

                                  14

                                          15

                                                  16

                                                            17

                                                                  18

                                                                           19

                                                                                    20

                                                                                           21

                                                                                                  22

                                                                                                         23

                                                                                                                24




                                                                                                                                                             13

                                                                                                                                                                     14

                                                                                                                                                                           15

                                                                                                                                                                                 16

                                                                                                                                                                                         17

                                                                                                                                                                                               18

                                                                                                                                                                                                        19

                                                                                                                                                                                                               20

                                                                                                                                                                                                                      21

                                                                                                                                                                                                                             22

                                                                                                                                                                                                                                    23

                                                                                                                                                                                                                                           24
                          SNB

                                  SPB

                                          GLB

                                                  SHB

                                                            GHB

                                                                  GHC

                                                                           SHC

                                                                                    GLC

                                                                                           SPC

                                                                                                  SNC

                                                                                                         SOC

                                                                                                                SOB




                                                                                                                                                             SNB

                                                                                                                                                                     SPB

                                                                                                                                                                           GLB

                                                                                                                                                                                 SHB

                                                                                                                                                                                         GHB

                                                                                                                                                                                               GHC

                                                                                                                                                                                                        SHC

                                                                                                                                                                                                               GLC

                                                                                                                                                                                                                      SPC

                                                                                                                                                                                                                             SNC

                                                                                                                                                                                                                                    SOC

                                                                                                                                                                                                                                           SOB
                                                                                                                            Not to scale                                                                                                               Not to scale

 Figure 6-7. DRV8323RH RGZ Package 48-Pin VQFN Figure 6-8. DRV8323RS RGZ Package 48-Pin VQFN
        With Exposed Thermal Pad Top View             With Exposed Thermal Pad Top View

                                                                         Table 6-4. Pin Functions—48-Pin DRV8323R Devices
                          PIN
                                    NO.                                           TYPE(1)                                                                    DESCRIPTION
 NAME
               DRV8323RH                        DRV8323RS
 AGND                35                                 35                         PWR            Device analog ground. Connect to system ground. AGND must be connected to BGND and PGND externally.
 BGND                43                                 43                         PWR            Buck regulator ground. Connect to system ground. BGND must be connected to AGND and PGND externally.
 CAL                 34                                 34                            I           Amplifier calibration input. Set logic high to internally short amplifier inputs and perform auto offset calibration.
 CB                  44                                 44                         PWR            Buck regulator bootstrap input. Connect an X5R or X7R, 0.1µF, 16V, capacitor between the CB and SW pins.
 CPH                  4                                 4                          PWR            Charge pump switching node. Connect an X5R or X7R, 47-nF, VM-rated ceramic capacitor between the CPH and CPL pins.
 CPL                  3                                 3                          PWR            For example, in a 24V system the capacitor should be rated 50V (2x margin).

 DGND                27                                 27                         PWR            Device ground. Connect to system ground.
                                                                                                  3.3V internal regulator output. Connect an X5R or X7R, 1µF, 6.3V ceramic capacitor between the DVDD and AGND pins. This
 DVDD                36                                 36                         PWR
                                                                                                  regulator can source up to 30mA externally.
                                                                                                  Gate driver enable. When this pin is logic low the device goes to a low-power sleep mode. An 8 to 40µs low pulse can be used
 ENABLE              33                                 33                            I
                                                                                                  to reset fault conditions without entering sleep mode.
 FB                   1                                 1                             I           Buck feedback input. A resistor divider from the buck post inductor output to this pin sets the buck output voltage.
 GAIN                32                                 —                             I           Amplifier gain setting. The pin is a 4 level input pin set by an external resistor.
 GHA                  8                                 8                           O             High-side gate driver output. Connect to the gate of the high-side power MOSFET.
 GHB                 17                                 17                          O             High-side gate driver output. Connect to the gate of the high-side power MOSFET.
 GHC                 18                                 18                          O             High-side gate driver output. Connect to the gate of the high-side power MOSFET.
 GLA                 10                                 10                          O             Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
 GLB                 15                                 15                          O             Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
 GLC                 20                                 20                          O             Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
 IDRIVE              30                                 —                             I           Gate drive output current setting. This pin is a 7 level input pin set by an external resistor.
 INHA                37                                 37                            I           High-side gate driver control input. This pin controls the output of the high-side gate driver when using 6x PWM mode.
 INHB                39                                 39                            I           High-side gate driver control input. This pin controls the output of the high-side gate driver when using 6x PWM mode.



10        Submit Document Feedback                                                                                                                                                     Copyright © 2026 Texas Instruments Incorporated

                                                                                  Product Folder Links: DRV8320 DRV8320R DRV8323 DRV8323R
                                                                                                                      DRV8320, DRV8320R, DRV8323, DRV8323R
www.ti.com                                                                                                            SLVSDJ3D – FEBRUARY 2017 – REVISED MARCH 2022

                                   Table 6-4. Pin Functions—48-Pin DRV8323R Devices (continued)
                     PIN
                           NO.               TYPE(1)                                                              DESCRIPTION
 NAME
            DRV8323RH            DRV8323RS
 INHC           41                  41          I      High-side gate driver control input. This pin controls the output of the high-side gate driver when using 6x PWM mode.
 INLA           38                  38          I      Low-side gate driver control input. This pin controls the output of the low-side gate driver when using 6x PWM mode.
 INLB           40                  40          I      Low-side gate driver control input. This pin controls the output of the low-side gate driver when using 6x PWM mode.
 INLC           42                  42          I      Low-side gate driver control input. This pin controls the output of the low-side gate driver when using 6x PWM mode.
 MODE           29                  —           I      PWM input mode setting. This pin is a 4 level input pin set by an external resistor.
 NC             46                  46         NC      No internal connection. This pin can be left floating or connected to system ground.
 nFAULT         28                  28         OD      Fault indicator output. This open drain pin pulls logic low during a fault condition and requires an external pullup resistor.
 nSCS           —                   32          I      Serial chip select. A logic low on this pin enables serial interface communication.
                                                       Buck shutdown input. Enable and disable input (high voltage tolerant). Internal pullup current source. Pull lower than 1.25V to
 nSHDN          48                  48          I
                                                       disable. Float to enable. Establish input undervoltage lockout with two resistor divider.
                                                       Device power ground. Also used as the gate drive sink path for the low side MOSFETs. Connect to system ground. PGND
 PGND           2                    2        PWR
                                                       must be connected to AGND and BGND externally.
 SCLK           —                   31          I      Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin.
 SDI            —                   30          I      Serial data input. Data is captured on the falling edge of the SCLK pin.
                                                       Serial data output. Data is shifted out on the rising edge of the SCLK pin. This open drain pin requires an external pullup
 SDO            —                   29         OD
                                                       resistor.
                                                       High-side source pin. Connect to the high-side power MOSFET source. This pin is an input for the VDS monitor and the
 SHA            9                    9         I/O
                                                       output for the high-side gate driver sink.
                                                       High-side source pin. Connect to the high-side power MOSFET source. This pin is an input for the VDS monitor and the
 SHB            16                  16         I/O
                                                       output for the high-side gate driver sink.
                                                       High-side source pin. Connect to the high-side power MOSFET source. This pin is an input for the VDS monitor and the
 SHC            19                  19         I/O
                                                       output for the high-side gate driver sink.
 SNA            12                  12          I      Current sense amplifier input. Connect to the low-side of the current shunt resistor. If CSA is not used tie to PGND.
 SNB            13                  13          I      Current sense amplifier input. Connect to the low-side of the current shunt resistor. If CSA is not used tie to PGND.
 SNC            22                  22          I      Current sense amplifier input. Connect to the low-side of the current shunt resistor. If CSA is not used tie to PGND.
 SOA            25                  25         O       Current sense amplifier output. If CSA is not used leave this pin disconnected.
 SOB            24                  24         O       Current sense amplifier output. If CSA is not used leave this pin disconnected.
 SOC            23                  23         O       Current sense amplifier output. If CSA is not used leave this pin disconnected.
                                                       Low-side current shunt amplifier input. Also VDS monitor negative input for low side MOSFET. Connect to the low-side power
 SPA            11                  11          I
                                                       MOSFET source and high-side of the current shunt resistor. If CSA is not used tie to SNA.
                                                       Low-side current shunt amplifier input. Also VDS monitor negative input for low side MOSFET. Connect to the low-side power
 SPB            14                  14          I
                                                       MOSFET source and high-side of the current shunt resistor. If CSA is not used tie to SNB.
                                                       Low-side current shunt amplifier input. Also VDS monitor negative input for low side MOSFET. Connect to the low-side power
 SPC            21                  21          I
                                                       MOSFET source and high-side of the current shunt resistor. If CSA is not used tie to SNC.
 SW             45                  45         O       Buck switch node. Connect this pin to an inductor, diode, and the CB bootstrap capacitor.
 VCP            5                    5        PWR      Charge pump output. Connect an X5R or X7R, 1µF, 25V ceramic capacitor between the VCP and VM pins.
                                                       High-side MOSFET drain input. Connect to the common point of the high-side MOSFET drains. This pin is an input for the
 VDRAIN         7                    7          I
                                                       VDS monitor.
 VDS            31                  —           I      VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor.
 VIN            47                  47        PWR      Buck regulator power supply input. Place an X5R or X7R, VM-rated ceramic capacitor between the VIN and BGND pins.
                                                       Gate driver power supply input. Connect to the motoro power supply and VDRAIN. Connect an X5R or X7R, 0.1µF, VM-rated
 VM             6                    6        PWR
                                                       ceramic and greater then or equal to 10uF local capacitance between the VM and PGND pins.
                                                       Current sense amplifier power supply input and reference. Connect an X5R or X7R, 0.1µF, 6.3V ceramic capacitor between
 VREF           26                  26        PWR
                                                       the VREF and AGND pins.
 Thermal
               PAD                 PAD        PWR      Must be connected to ground
 Pad


(1)     PWR = power, I = input, O = output, NC = no connection, OD = open-drain output




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7 Specifications
7.1 Absolute Maximum Ratings
at TA = –40°C to +125°C (unless otherwise noted)(1)
                                                                                                   MIN              MAX              UNIT
 GATE DRIVER
 Power supply pin voltage (VM)                                                                     –0.3               65               V
 Voltage differential between ground pins (AGND, BGND, DGND, PGND)                                 –0.3              0.3               V
 MOSFET drain sense pin voltage (VDRAIN)                                                           –0.3               65               V
 Charge pump pin voltage (CPH, VCP)                                                                –0.3          VVM + 15.5            V
 Continuous charge pump negative-switching pin voltage (CPL)                                       –0.3            VVM + 1             V
 Transient 1-us charge pump negative-switching pin voltage (CPL)                                    –1                                 V
 Internal logic regulator pin voltage (DVDD)                                                       –0.3              3.8               V
 Digital pin voltage (CAL, ENABLE, GAIN, IDRIVE, INHx, INLx, MODE, nFAULT, nSCS,
                                                                                                   –0.3              5.75              V
 SCLK, SDI, SDO, VDS)
                                                                                                                   VVCP +
 Continuous high-side gate driver output pin voltage (GHx)                                        –5(2)                                V
                                                                                                                     1
                                                                                                                   VVCP +
 Transient 200ns high-side gate driver output pin voltage (GHx)                                     –7                                 V
                                                                                                                     1
 High-side gate driver output pin voltage with respect to SHx (GHx)                                –1.6               18               V
 Continuous high-side source pin voltage (SHx)                                                    –5(2)            VVM + 5             V
 Transient 200ns high-side source pin voltage (SHx)                                                 –7             VVM + 7             V
 Transient 1-us high-side source pin voltage (SHx)                                                                 VVCP - 2            V

 Continuous low-side gate driver output pin voltage (GLx)                                          –0.5               18               V

 Transient 200ns low-side gate driver output pin voltage (GLx)                                     –1.5                                V
 Gate driver output pin source current (GHx, GLx)                                                    Internally limited                A
 Gate driver output pin sink current (GHx, GLx)                                                      Internally limited                A
 Continuous voltage at low-side source pin (SLx) and current sense amplifier input pin
                                                                                                    –1                1                V
 (SPx, SNx)
 Transient 200ns voltage at low-side source pin (SLx) and current sense amplifier input pin
                                                                                                    –3                3                V
 (SPx, SNx)
 Current sense amplifier power supply input and reference pin voltage (VREF)                       –0.3              5.75              V
 Current sense amplifier output pin voltage (SOx)                                                  –0.3          VVREF + 0.3           V
 BUCK REGULATOR
 Power supply pin voltage (VIN)                                                                    –0.3               65               V
 Shutdown control pin voltage (nSHDN)                                                              –0.3              VVIN              V
 Voltage feedback pin voltage (FB)                                                                 –0.3               7                V
 Bootstrap pin voltage with respect to SW (CB)                                                     –0.3               7                V
 Switching node pin voltage (SW)                                                                   –0.3              VVIN              V
 Switching node pin voltage less than 30ns transients (SW)                                          –2               VVIN              V
 DRV832x
 Operating junction temperature, TJ                                                                –40               150               °C
 Storage temperature, Tstg                                                                         –65               150               °C

(1)   Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
      ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
      Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
      reliability.



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(2)     Continuous high-side gate driver output pin (GHx) and high-side source pin voltage (SHx) should be limited to –2V minimum for an
        absolute maximum of 65V on VM or VDRAIN. At 60V and lower, the full specification of –5V continuous on GHx and SHx is allowable.


7.2 ESD Ratings
                                                                                                                    VALUE        UNIT

             Electrostatic            Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)                         ±3000
 V(ESD)                                                                                                                            V
             discharge                Charged-device model (CDM), per JEDEC specification JESD22-C101(2)            ±1000

(1)     JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
        ±2000V may actually have higher performance.
(2)     JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process. Pins listed as
        ±500V may actually have higher performance.


7.3 Recommended Operating Conditions
at TA = –40°C to +125°C (unless otherwise noted)
                                                                                                       MIN            MAX       UNIT
 GATE DRIVER
 VVM               Power supply voltage (VM)                                                                6              60     V
                   Input voltage (CAL, ENABLE, GAIN, IDRIVE, INHx, INLx, MODE, nSCS,
 VI                                                                                                         0          5.5        V
                   SCLK, SDI, VDS)
 fPWM              Applied PWM signal (INHx, INLx)                                                          0        200(1)      kHz
 IGATE_HS          High-side average gate drive current (GHx)                                               0         25(1)      mA
 IGATE_LS          Low-side average gate drive current (GLx)                                                0         25(1)      mA
 IDVDD             External load current (DVDD)                                                             0         30(1)      mA
 VVREF             Current sense amplifier power supply input and reference (VREF)                          3          5.5        V
 ISO               Current sense amplifier output current (SOx)                                             0               5    mA
 VOD               Open drain pin pullup voltage (nFAULT, SDO)                                              0          5.5        V
 IOD               Open drain pin output current (nFAULT, SDO)                                              0               5    mA
 BUCK REGULATOR
 VVIN              Power supply voltage (VIN)                                                               4              60     V
 VnSHDN            Shutdown control input voltage (nSHDN)                                                   0              60     V
 DRV832x
 TA                Operating ambient temperature                                                       –40             125       °C

(1)     Power dissipation and thermal limits must be observed

7.4 Thermal Information
                                                                                                 DRV832x
                                                                             RTV          RHA           RTA           RGZ
                             THERMAL METRIC(1)                                                                                   UNIT
                                                                           (WQFN)        (VQFN)       (WQFN)        (VQFN)
                                                                           32 PINS      40 PINS       40 PINS       48 PINS
 RθJA       Junction-to-ambient thermal resistance                           32.9         30.1         32.1          26.6        °C/W
 RθJC(top) Junction-to-case (top) thermal resistance                         15.8         16.7             11        13.9        °C/W
 RθJB       Junction-to-board thermal resistance                              6.8          9.9             7.1        9.2        °C/W
 ψJT        Junction-to-top characterization parameter                        0.2          0.5             0.1        0.3        °C/W
 ψJB        Junction-to-board characterization parameter                      6.8          9.9             7.1        9.1        °C/W
 RθJC(bot) Junction-to-case (bottom) thermal resistance                       2.1          2.2             2.1         2         °C/W

(1)     For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
        report.




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7.5 Electrical Characteristics
at TA = –40°C to +125°C, VVM = 6 to 60V (unless otherwise noted)
                    PARAMETER                                     TEST CONDITIONS                           MIN     TYP      MAX     UNIT
 POWER SUPPLIES (DVDD, VCP, VM)
 IVM              VM operating supply current      VVM = 24V, ENABLE = 3.3V, INHx/INLx = 0                          10.5       14     mA
                                                   ENABLE = 0V, VVM = 24V, TA = 25°C                                   12      20
 IVMQ             VM sleep mode supply current                                                                                         µA
                                                   ENABLE = 0V, VVM = 24V, TA = 125°C(1)                                       50
 tRST (1)         Reset pulse time                 ENABLE = low period to reset faults                         8               40      µs
 tWAKE            Wake up time                     VVM > VUVLO, ENABLE = 3.3V to outputs ready                                   1     ms

 tSLEEP           Sleep time                       ENABLE = 0V to device sleep mode                                              1     ms
 VDVDD            DVDD regulator voltage           IDVDD = 0 to 30mA                                           3      3.3      3.6     V
                                                   VVM = 13V, IVCP = 0 to 25mA                               8.4       11    12.5

                  VCP operating voltage            VVM = 10V, IVCP = 0 to 20mA                               6.3        9      10
 VVCP                                                                                                                                  V
                  with respect to VM               VVM = 8V, IVCP = 0 to 15mA                                5.4        7        8
                                                   VVM = 6V, IVCP = 0 to 10mA                                  4        5        6
 LOGIC-LEVEL INPUTS (CAL, ENABLE, INHx, INLx, nSCS, SCLK, SDI)
 VIL              Input logic low voltage                                                                      0               0.8     V
 VIH              Input logic high voltage                                                                   1.5               5.5     V
 VHYS             Input logic hysteresis                                                                             100              mV
 IIL              Input logic low current          VVIN = 0V                                                  –5                 5     µA
 IIH              Input logic high current         VVIN = 5V                                                           50      70      µA
 RPD              Pulldown resistance              To AGND                                                           100               kΩ
 tPD              Propagation delay                INHx/INLx transition to GHx/GLx transition                        150               ns
 FOUR-LEVEL H/W INPUTS (GAIN, MODE)
 VI1              Input mode 1 voltage             Tied to AGND                                                         0              V
 VI2              Input mode 2 voltage             45kΩ ± 5% tied to AGND                                             1.2              V
 VI3              Input mode 3 voltage             Hi-Z                                                                 2              V
 VI4              Input mode 4 voltage             Tied to DVDD                                                       3.3              V
 RPU              Pullup resistance                Internal pullup to DVDD                                             50              kΩ
 RPD              Pulldown resistance              Internal pulldown to AGND                                           84              kΩ
 SEVEN-LEVEL H/W INPUTS (IDRIVE, VDS)
 VI1              Input mode 1 voltage             Tied to AGND                                                         0              V
 VI2              Input mode 2 voltage             18kΩ ± 5% tied to AGND                                             0.5              V
 VI3              Input mode 3 voltage             75kΩ ± 5% tied to AGND                                             1.1              V
 VI4              Input mode 4 voltage             Hi-Z                                                             1.65               V
 VI5              Input mode 5 voltage             75kΩ ± 5% tied to DVDD                                             2.2              V
 VI6              Input mode 6 voltage             18kΩ ± 5% tied to DVDD                                             2.8              V
 VI7              Input mode 7 voltage             Tied to DVDD                                                       3.3              V
 RPU              Pullup resistance                Internal pullup to DVDD                                             73              kΩ
 RPD              Pulldown resistance              Internal pulldown to AGND                                           73              kΩ
 OPEN DRAIN OUTPUTS (nFAULT, SDO)
 VOL              Output logic low voltage         IO = 5mA                                                                    0.1     V
 IOZ              Output high impedance leakage    VO = 5V                                                    –2                 2     µA
 GATE DRIVERS (GHx, GLx)




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7.5 Electrical Characteristics (continued)
at TA = –40°C to +125°C, VVM = 6 to 60V (unless otherwise noted)
                     PARAMETER                                          TEST CONDITIONS                   MIN    TYP    MAX    UNIT
                                                        VVM = 13V, IVCP = 0 to 25mA                        8.4     11   12.5

                    High-side gate drive voltage        VVM = 10V, IVCP = 0 to 20mA                        6.3      9     10
 VGSH (1)                                                                                                                         V
                    with respect to SHx                 VVM = 8V, IVCP = 0 to 15mA                         5.4      7      8
                                                        VVM = 6V, IVCP = 0 to 10mA                           4      5      6
                                                        VVM = 12V, IVGLS = 0 to 25mA                         9     11     12

                    Low-side gate drive voltage         VVM = 10V, IVGLS = 0 to 20mA                       7.5      9     10
 VGSL (1)                                                                                                                         V
                    with respect to PGND                VVM = 8V, IVGLS = 0 to 15mA                        5.5      7      8
                                                        VVM = 6V, IVGLS = 0 to 10mA                          4      5      6
                                                        DEAD_TIME = 00b                                            50
                                                        DEAD_TIME = 01b                                           100
                    Gate drive             SPI Device
 tDEAD                                                  DEAD_TIME = 10b                                           200             ns
                    dead time
                                                        DEAD_TIME = 11b                                           400
                                           H/W Device                                                             100
                                                        TDRIVE = 00b                                              500
                                                        TDRIVE = 01b                                             1000
                    Peak current           SPI Device
 tDRIVE                                                 TDRIVE = 10b                                             2000             ns
                    gate drive time
                                                        TDRIVE = 11b                                             4000
                                           H/W Device                                                            4000
                                                        IDRIVEP_HS or IDRIVEP_LS = 0000b                           10
                                                        IDRIVEP_HS or IDRIVEP_LS = 0001b                           30
                                                        IDRIVEP_HS or IDRIVEP_LS = 0010b                           60
                                                        IDRIVEP_HS or IDRIVEP_LS = 0011b                           80
                                                        IDRIVEP_HS or IDRIVEP_LS = 0100b                          120
                                                        IDRIVEP_HS or IDRIVEP_LS = 0101b                          140
                                                        IDRIVEP_HS or IDRIVEP_LS = 0110b                          170
                                                        IDRIVEP_HS or IDRIVEP_LS = 0111b                          190
                                           SPI Device
                                                        IDRIVEP_HS or IDRIVEP_LS = 1000b                          260
                                                        IDRIVEP_HS or IDRIVEP_LS = 1001b                          330
                                                        IDRIVEP_HS or IDRIVEP_LS = 1010b                          370
                    Peak source
 IDRIVEP                                                IDRIVEP_HS or IDRIVEP_LS = 1011b                          440           mA
                    gate current
                                                        IDRIVEP_HS or IDRIVEP_LS = 1100b                          570
                                                        IDRIVEP_HS or IDRIVEP_LS = 1101b                          680
                                                        IDRIVEP_HS or IDRIVEP_LS = 1110b                          820
                                                        IDRIVEP_HS or IDRIVEP_LS = 1111b                         1000
                                                        IDRIVE = Tied to AGND                                      10
                                                        IDRIVE = 18kΩ ± 5% tied to AGND                            30
                                                        IDRIVE = 75kΩ ± 5% tied to AGND                            60
                                           H/W Device   IDRIVE = Hi-Z                                             120
                                                        IDRIVE = 75kΩ ± 5% tied to DVDD                           260
                                                        IDRIVE = 18kΩ ± 5% tied to DVDD                           570
                                                        IDRIVE = Tied to DVDD                                    1000




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7.5 Electrical Characteristics (continued)
at TA = –40°C to +125°C, VVM = 6 to 60V (unless otherwise noted)
                    PARAMETER                                           TEST CONDITIONS                MIN     TYP      MAX     UNIT
                                                        IDRIVEN_HS or IDRIVEN_LS = 0000b                          20
                                                        IDRIVEN_HS or IDRIVEN_LS = 0001b                          60
                                                        IDRIVEN_HS or IDRIVEN_LS = 0010b                        120
                                                        IDRIVEN_HS or IDRIVEN_LS = 0011b                        160
                                                        IDRIVEN_HS or IDRIVEN_LS = 0100b                        240
                                                        IDRIVEN_HS or IDRIVEN_LS = 0101b                        280
                                                        IDRIVEN_HS or IDRIVEN_LS = 0110b                        340
                                                        IDRIVEN_HS or IDRIVEN_LS = 0111b                        380
                                           SPI Device
                                                        IDRIVEN_HS or IDRIVEN_LS = 1000b                        520
                                                        IDRIVEN_HS or IDRIVEN_LS = 1001b                        660
                                                        IDRIVEN_HS or IDRIVEN_LS = 1010b                        740
                  Peak sink
 IDRIVEN                                                IDRIVEN_HS or IDRIVEN_LS = 1011b                        880              mA
                  gate current
                                                        IDRIVEN_HS or IDRIVEN_LS = 1100b                       1140
                                                        IDRIVEN_HS or IDRIVEN_LS = 1101b                       1360
                                                        IDRIVEN_HS or IDRIVEN_LS = 1110b                       1640
                                                        IDRIVEN_HS or IDRIVEN_LS = 1111b                       2000
                                                        IDRIVE = Tied to AGND                                     20
                                                        IDRIVE = 18kΩ ± 5% tied to AGND                           60
                                                        IDRIVE = 75kΩ ± 5% tied to AGND                         120
                                           H/W Device   IDRIVE = Hi-Z                                           240
                                                        IDRIVE = 75kΩ ± 5% tied to DVDD                         520
                                                        IDRIVE = 18kΩ ± 5% tied to DVDD                        1140
                                                        IDRIVE = Tied to DVDD                                  2000
                                                        Source current after tDRIVE                               10
 IHOLD            Gate holding current                                                                                           mA
                                                        Sink current after tDRIVE                                 50
 ISTRONG          Gate strong pulldown current          GHx to SHx and GLx to PGND                                 2              A
                                                        GHx to SHx                                              480
 ROFF             Gate hold off resistor                                                                                          kΩ
                                                        GLx to PGND                                             150
 CURRENT SENSE AMPLIFIER (SNx, SOx, SPx, VREF)
                                                        CSA_GAIN = 00b                                 4.85        5    5.15
                                                        CSA_GAIN = 01b                                  9.7       10    10.3
                                           SPI Device
                                                        CSA_GAIN = 10b                                 19.4       20    20.6
                                                        CSA_GAIN = 11b                                 38.8       40    41.2
 GCSA             Amplifier gain                                                                                                 V/V
                                                        GAIN = Tied to AGND                            4.85        5    5.15
                                                        GAIN = 47kΩ ± 5% tied to AGND                   9.7       10    10.3
                                           H/W Device
                                                        GAIN = Hi-Z                                    19.4       20    20.6
                                                        GAIN = Tied to DVDD                            38.8       40    41.2
                                                        VO_STEP = 0.5V, GCSA = 5V/V                             150
                                                        VO_STEP = 0.5V, GCSA = 10V/V                            300
 tSET (1)         Settling time to ±1%                                                                                            ns
                                                        VO_STEP = 0.5V, GCSA = 20V/V                            600
                                                        VO_STEP = 0.5V, GCSA = 40V/V                           1200
 VCOM             Common mode input range                                                            –0.15              0.15      V
 VDIFF            Differential mode input range                                                        –0.3               0.3     V


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7.5 Electrical Characteristics (continued)
at TA = –40°C to +125°C, VVM = 6 to 60V (unless otherwise noted)
                     PARAMETER                                          TEST CONDITIONS                   MIN       TYP      MAX     UNIT
 VOFF               Input offset error                  VSP = VSN = 0V, CAL = 3.3 , VREF = 3.3V             –4                  4     mV
 VDRIFT   (1)       Drift offset                        VSP = VSN = 0V                                                10             µV/°C
                                                                                                                            VVREF
 VLINEAR            SOx output voltage linear range                                                       0.25                        V
                                                                                                                            – 0.25
                                                        VSP = VSN = 0V, CAL = 3.3V, VREF_DIV = 0b            VVREF – 0.3
                    SOx output voltage SPI Device
 VBIAS                                                  VSP = VSN = 0V, CAL = 3.3 , VREF_DIV = 1b             VVREF / 2               V
                    bias
                                       H/W Device       VSP = VSN = 0V, CAL = 3.3V                            VVREF / 2
 IBIAS              SPx/SNx input bias current          VREF_DIV = 1b                                                         100     µA
 VSLEW    (1)       SOx output slew rate                60pF load                                                     10             V/µs
 IVREF              VREF input current                  VVREF = 5V                                                     2        3     mA
 UGB(1)             Unity gain bandwidth                60pF load                                                     10             MHz
 PROTECTION CIRCUITS
                                                        VM falling, UVLO report                            5.4       5.6      5.8
 VUVLO              VM undervoltage lockout                                                                                           V
                                                        VM rising, UVLO recovery                           5.6       5.8        6
 VUVLO_HYS          VM undervoltage hysteresis          Rising to falling threshold                                 200               mV
 tUVLO_DEG          VM undervoltage deglitch time       VM falling, UVLO report                                       10              µs
                    Charge pump undervoltage
 VCPUV                                                  VCP falling, CPUV report                              VVM + 2.8               V
                    lockout
                                                        Positive clamping voltage                           15      16.5       18
 VGS_CLAMP          High-side gate clamp                                                                                              V
                                                        Negative clamping voltage                                   –0.7
                                                        VDS_LVL = 0000b                                             0.06
                                                        VDS_LVL = 0001b                                             0.13
                                                        VDS_LVL = 0010b                                              0.2
                                                        VDS_LVL = 0011b                                             0.26
                                                        VDS_LVL = 0100b                                             0.31
                                                        VDS_LVL = 0101b                                             0.45
                                                        VDS_LVL = 0110b                                             0.53
                                                        VDS_LVL = 0111b                                              0.6
                                           SPI Device
                                                        VDS_LVL = 1000b                                             0.68
                                                        VDS_LVL = 1001b                                             0.75
                                                        VDS_LVL = 1010b                                             0.94
                    VDS overcurrent
 VVDS_OCP                                               VDS_LVL = 1011b                                             1.13              V
                    trip voltage
                                                        VDS_LVL = 1100b                                              1.3
                                                        VDS_LVL = 1101b                                              1.5
                                                        VDS_LVL = 1110b                                              1.7
                                                        VDS_LVL = 1111b                                             1.88
                                                        VDS = Tied to AGND                                          0.06
                                                        VDS = 18kΩ ± 5% tied to AGND                                0.13
                                                        VDS = 75kΩ ± 5% tied to AGND                                0.26
                                           H/W Device   VDS = Hi-Z                                                   0.6
                                                        VDS = 75kΩ ± 5% tied to DVDD                                1.13
                                                        VDS = 18kΩ ± 5% tied to DVDD                                1.88
                                                        VDS = Tied to DVDD                                       Disabled




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7.5 Electrical Characteristics (continued)
at TA = –40°C to +125°C, VVM = 6 to 60V (unless otherwise noted)
                       PARAMETER                                          TEST CONDITIONS                        MIN     TYP      MAX     UNIT
                                                          OCP_DEG = 00b                                                      2
                                                          OCP_DEG = 01b                                                      4
                     VDS and VSENSE       SPI Device
 tOCP_DEG            overcurrent deglitch                 OCP_DEG = 10b                                                      6              µs
                     time
                                                          OCP_DEG = 11b                                                      8
                                           H/W Device                                                                        4
                                                          SEN_LVL = 00b                                                  0.25
                                                          SEN_LVL = 01b                                                    0.5
                     VSENSE overcurrent SPI Device
 VSEN_OCP                                                 SEN_LVL = 10b                                                  0.75               V
                     trip voltage
                                                          SEN_LVL = 11b                                                      1
                                           H/W Device                                                                        1
                                                          TRETRY = 0b                                                        4              ms
                     Overcurrent retry     SPI Device
 tRETRY                                                   TRETRY = 1b                                                       50              μs
                     time
                                           H/W Device                                                                        4              ms
 TOTW (1)            Thermal warning temperature          Die temperature, TJ                                    130      150      165      °C
 TOTSD     (1)       Thermal shutdown temperature         Die temperature, TJ                                    150      170      185      °C
 THYS (1)            Thermal hysteresis                   Die temperature, TJ                                               20              °C
 BUCK REGULATOR SUPPLY (VIN)
 InSHDN              Shutdown supply current              VnSHDN = 0V                                                        1        3     µA
 IQ                  Operating quiescent current          VVIN = 12V, no load; not switching                                28              µA

                     VIN undervoltage lockout             VIN Rising                                                                  4
 VVIN_UVLO                                                                                                                                  V
                     threshold                            VIN Falling                                               3
 BUCK REGULATOR SHUTDOWN (nSHDN)
 VnSHDN_TH           Rising nSHDN threshold                                                                      1.05    1.25     1.38      V
                                                          VnSHDN = 2.3V                                                  –4.2
 InSHDN              Input current                                                                                                          µA
                                                          VnSHDN = 0.9V                                                     –1
 InSHDN_HYS          Hysteresis current                                                                                     –3              µA
 BUCK REGULATOR HIGH-SIDE MOSFET
 RDS_ON              MOSFET on resistance                 VVIN = 12V, VCB to VSW = 5.8V, TA = 25°C                        900              mΩ
 BUCK REGULATOR VOLTAGE REFERENCE (FB)
 VFB                 Feedback voltage                                                                          0.747    0.765    0.782      V
 BUCK REGULATOR CURRENT LIMIT
                                                          VVIN = 12V, TA = 25°C                                          1200
 ILIMIT              Peak current limit                                                                                                    mA
                                                                                                                                  1700
 BUCK REGULATOR SWITCHING (SW)
 fSW                 Switching frequency                                                                         595      700      805     kHz
 DMAX                Maximum duty cycle                                                                                  96%
 BUCK REGULATOR THERMAL SHUTDOWN
 TSHDN (1)           Thermal shutdown threshold                                                                           170               °C
 THYS     (1)        Thermal shutdown hysteresis                                                                            10              °C

(1)       Specified by design and characterization data




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7.6 SPI Timing Requirements
at TA = –40°C to +125°C, VVM = 6 to 60V (unless otherwise noted) (1)
                                                                                                                              MIN   NOM         MAX        UNIT
 SPI (nSCS, SCLK, SDI, SDO)
 tREADY                SPI ready after enable                             VM > UVLO, ENABLE = 3.3V                                                     1   ms
 tCLK                  SCLK minimum period                                                                                    100                           ns
 tCLKH                 SCLK minimum high time                                                                                  50                           ns
 tCLKL                 SCLK minimum low time                                                                                   50                           ns
 tSU_SDI               SDI input data setup time                                                                               20                           ns
 tH_SDI                SDI input data hold time                                                                                30                           ns
 tD_SDO                SDO output data delay time                         SCLK high to SDO valid                                                   30       ns
 tSU_nSCS              nSCS input setup time                                                                                   50                           ns
 tH_nSCS               nSCS input hold time                                                                                    50                           ns
 tHI_nSCS              nSCS minimum high time before active low                                                               400                           ns
 tDIS_nSCS             nSCS disable time                                  nSCS high to SDO high impedance                                 10                ns

(1)      Specified by design and characterization data
               tHI_nSCS   tSU_nSCS                                                                                              tH_nSCS


  nSCS


                                                          tCLK


  SCLK

                                              tCLKH                    tCLKL



   SDI        X                       MSB                                                                         LSB                             X
                                                      tSU_SDI tH_SDI



  SDO              Z                             MSB                                                                    LSB                                Z

                                     tD_SDO                                                                                                tDIS_nSCS



                                                        Figure 7-1. SPI Slave Mode Timing Diagram




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7.7 Typical Characteristics
                             16                                                                                          15

                             14                                                                                          14
                                                                                                                         13
                             12
       Supply Current (mA)




                                                                                                   Supply Current (mA)
                                                                                                                         12
                             10                                                                                          11
                              8                                                                                          10

                              6                                                                                           9
                                                                                                                          8
                              4
                                                                              TA = 40qC                                   7                                                       VVM = 6 V
                              2                                               TA = 25qC                                   6                                                       VVM = 24 V
                                                                              TA = 125qC                                                                                          VVM = 60 V
                              0                                                                                           5
                                  0        10        20       30        40    50       60                                 -40         -20        0    20    40    60     80   100     120   140
                                                       Supply Voltage (V)                  D001
                                                                                                                                                     Ambient Temperature (°C)                   D002
                                          Figure 7-2. Supply Current Over VM                                                      Figure 7-3. Supply Current Over Temperature
                             24                                                                                          24
                             22                                                                                          22
                             20                                                                                          20
                             18                                                                                          18
      Sleep Current (PA)




                                                                                                   Sleep Current (PA)
                             16                                                                                          16
                             14                                                                                          14
                             12                                                                                          12
                             10                                                                                          10
                              8                                                                                           8
                              6                                                                                           6
                              4                                               TA = 40qC                                   4                                                       VVM = 6 V
                                                                              TA = 25qC                                                                                           VVM = 24 V
                              2                                               TA = 125qC                                  2                                                       VVM = 60 V
                              0                                                                                           0
                                  0        10        20       30        40    50       60                                 -40         -20        0    20    40    60     80   100     120   140
                                                       Supply Voltage (V)                  D003
                                                                                                                                                     Ambient Temperature (qC)                   D004
                                          Figure 7-4. Sleep Current Over VM                                                       Figure 7-5. Sleep Current Over Temperature
                                  4                                                                                           4
                                                                              TA = 40qC                                                                                            TA = 40qC
                             3.75                                             TA = 25qC                                  3.75                                                      TA = 25qC
                                                                              TA = 125qC                                                                                           TA = 125qC
                              3.5                                                                                         3.5
     DVDD Voltage (V)




                                                                                                  DVDD Voltage (V)




                             3.25                                                                                        3.25

                                  3                                                                                           3

                             2.75                                                                                        2.75

                              2.5                                                                                         2.5

                             2.25                                                                                        2.25

                                  2                                                                                           2
                                      0     10        20       30        40    50      60                                         0         10         20       30        40        50       60
                                                        Supply Voltage (V)                 D005
                                                                                                                                                         Supply Voltage (V)                     D006

                                          0mA load                                                                                     30mA load

                                          Figure 7-6. DVDD Voltage Over VM                                                              Figure 7-7. DVDD Voltage Over VM




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7.7 Typical Characteristics (continued)
                      12                                                                                  14


                      10                                                                                  12

                                                                                                          10
    VCP Voltage (V)




                                                                                        VCP Voltage (V)
                       8
                                                                                                           8
                       6
                                                                                                           6
                       4
                                                                                                           4
                                                                    VVM = 6 V                                                                           VVM = 6 V
                       2                                            VVM = 8 V                                                                           VVM = 8 V
                                                                    VVM = 10 V                             2                                            VVM = 10 V
                                                                    VVM = 13 V                                                                          VVM = 13 V
                       0                                                                                   0
                           0   2.5   5   7.5     10 12.5 15 17.5   20   22.5   25                          -40    -20    0    20    40    60     80   100   120   140
                                               Load Current (mA)                 D007
                                                                                                                             Ambient Temperature (°C)                D008
                                 Figure 7-8. VCP Voltage Over Load                                                  0mA load

                                                                                                                 Figure 7-9. VCP Voltage Over Temperature




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8 Detailed Description
8.1 Overview
The DRV832x family of devices is an integrated 6 to 60-V gate driver for three-phase motor drive applications.
These devices decrease system component count, cost, and complexity by integrating three independent
halfbridge gate drivers, charge pump, and linear regulator for the supply voltages of the high-side and low-side
gate drivers.The device also integrates optional triple current shunt (or current sense) amplifiers and an optional
600-mA buck regulator. A standard serial peripheral interface (SPI) provides a simple method for configuring
the various device settings and reading fault diagnostic information through an external controller. Alternatively,
a hardware interface (H/W) option allows for configuring the most common settings through fixed external
resistors.
The gate drivers support external N-channel high-side and low-side power MOSFETs and can drive up to 1A
source, 2A sink peak currents with a 25mA average output current. A doubler charge pump generates the supply
voltage of the high-side gate drive. This charge pump architecture regulates the VCP output to VVM + 11V. The
supply voltage of the low-side gate driver is generated using a linear regulator from the VM power supply that
regulates to 11V. A Smart Gate Drive architecture provides the ability to dynamically adjust the strength of the
gate drive output current which lets the gate driver control the VDS switching speed of the power MOSFET. This
feature lets the user remove the external gate drive resistors and diodes, reducing the component count in the
bill of materials (BOM), cost, and area of the printed circuit board (PCB). The architecture also uses an internal
state machine to protect against short-circuit events in the gate driver, control the half-bridge dead time, and
protect against dV/dt parasitic turnon of the external power MOSFET.
The DRV8323 and DRV8323R devices integrate three bidirectional current sense amplifiers for monitoring the
current level through each of the external half-bridges using a low-side shunt resistor. The gain setting of
the current sense amplifier can be adjusted through the SPI or hardware interface. The SPI method provides
additional flexibility to adjust the output bias point.
The DRV8320R and DRV8323R devices integrate a 600mA buck regulator that can be used to power an
external controller or other logic circuits. The buck regulator is implemented as a separate internal die that can
use either the same or a different power supply than the gate driver.
In addition to the high level of device integration, the DRV832x family of devices provides a wide range of
integrated protection features. These features include power supply undervoltage lockout (UVLO), charge pump
undervoltage lockout (CPUV), VDS overcurrent monitoring (OCP), gate driver short-circuit detection (GDF), and
overtemperature shutdown (OTW and OTSD). Fault events are indicated by the nFAULT pin with detailed
information available in the SPI registers on the SPI device version.
The DRV832x family of devices are available in 0.5mm pin pitch, QFN surface-mount packages. The QFN sizes
are 5 × 5mm for the 32pin package, 6 × 6mm for the 40pin package, and 7 × 7mm for the 48pin package.




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8.2 Functional Block Diagram
  VM
                                                                                                                       VM
                                                                                                     VDRAIN
                          VM
                                                                               VCP
                                                                                                     GHA
                         VCP                                                   HS
                 1 …F
>10 …F 0.1 …F                             VCP                                                        SHA
                         CPH
                                         Charge                                VGLS
         47 nF                           Pump
                         CPL                                                                         GLA
                                                                               LS

                                                                                                     SLA
                                VGLS
                                         VGLS                               Gate Driver
                                         Linear
                                        Regulator
                                                                                                                       VM
                                                                               VCP
       30 mA            DVDD
                                         DVDD                                                        GHB
       1 …F                              Linear                                HS
                        AGND            Regulator
                                                                                                     SHB
                                          Power
                        PGND                                                   VGLS
                                                               Digital                               GLB
                   ENABLE                                                      LS
                                                               Core

                                                                                                     SLB
                        INHA
                                                                            Gate Driver


                         INLA                                                                                          VM
                                                             Smart Gate        VCP
                                                               Drive                                 GHC
                                                                               HS
                        INHB
                                                             Protection
                                                                                                     SHC
                         INLB                                                  VGLS
                                             Control
                                             Inputs                                                  GLC
                                                                               LS
                        INHC
                                                                                                     SLC
                                                                            Gate Driver                       VCC
                        INLC
                                                                                                                 RPU
                                                                            Fault Output             nFAULT
                        MODE

                    IDRIVE

                         VDS


                                                                                               Copyright © 2017, Texas Instruments Incorporated

                                                  Figure 8-1. Block Diagram for DRV8320H




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     VM                                                                                                          VM
                                                                                                VDRAIN
                           VM
                                                                              VCP
                                                                                                GHA
                           VCP                                                HS
                   1 …F
>10 …F 0.1 …F                             VCP                                                   SHA
                           CPH
                                         Charge                               VGLS
           47 nF                         Pump
                           CPL                                                                  GLA
                                                                              LS

                                                                                                SLA
                                 VGLS
                                         VGLS                              Gate Driver
                                         Linear
                                        Regulator
                                                                                                                 VM
          30 mA           DVDD                                                VCP
                                         DVDD
                                         Linear                                                 GHB
          1 …F                                                                HS
                          AGND          Regulator
                                          Power                                                 SHB
                          PGND
                                                                              VGLS

                     ENABLE                                 Digital                             GLB
                                                            Core              LS

                                                                                                SLB
                          INHA
                                                                           Gate Driver

                          INLA
                                                                                                                 VM
                                                          Smart Gate          VCP
                          INHB                              Drive                               GHC
                                             Control
                                                                              HS
                                             Inputs
                                                           Protection
                          INLB                                                                  SHC
                                                                              VGLS
                          INHC                                                                  GLC
                                                                              LS

                          INLC                                                                  SLC
                                                                           Gate Driver                 VCC

            VCC            SDI                                                                             RPU
                                              SPI                          Fault Output         nFAULT
                  RPU
                          SDO

                          SCLK


                          nSCS




                                                                                          Copyright © 2017, Texas Instruments Incorporated

                                               Figure 8-2. Block Diagram for DRV8320S




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  VM                                                                                                                    VM
                                                                                                     VDRAIN
                            VM
                                                                               VCP
                                                                                                     GHA
                           VCP                                                 HS
                   1 …F
>10 …F 0.1 …F                              VCP                                                       SHA
                           CPH
                                          Charge                               VGLS
                                          Pump
         47 nF
                           CPL                                                                       GLA
                                                                               LS

                                                                                                     SLA
                                  VGLS
                                          VGLS                              Gate Driver
                                          Linear
                                         Regulator
                                                                                                                        VM
          30 mA           DVDD                                                 VCP
                                          DVDD
          1 …F                            Linear                                                     GHB
                          AGND           Regulator                             HS

                                           Power                                                     SHB
                          PGND
                                                                               VGLS

                     ENABLE                                   Digital                                GLB
                                                              Core             LS

                                                                                                     SLB
                          INHA
                                                                            Gate Driver

                           INLA                                                                                         VM
                                                           Smart Gate          VCP
                                                             Drive                                   GHC
                          INHB
                                                                               HS
                                                            Protection
                                                                                                     SHC
                           INLB
                                              Control                          VGLS
                                              Inputs
                          INHC                                                                       GLC
                                                                               LS

                                                                                                     SLC
                          INLC
                                                                            Gate Driver                       VCC

                          MODE
                                                                                                                  RPU
                                                                            Fault Output             nFAULT
                      IDRIVE

                           VDS

             VIN
                           VIN                                                                       CB
                                                                                                              0.1 µF
                                                                                                                        LOUT
                      nSHDN                             Buck Regulator                               SW                        600 mA
       CIN
                                                        (LMR16006X)
                          BGND                                                                       FB    DOUT                     COUT
                                                                                                                        RFB1



                                                                                                                        RFB2


                                                                                               Copyright © 2017, Texas Instruments Incorporated

                                               Figure 8-3. Block Diagram for DRV8320RH




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     VM
                                                                                                                       VM
                                                                                                    VDRAIN
                               VM
                                                                                  VCP
                                                                                                    GHA
                               VCP                                                HS
                       1 …F
>10 …F 0.1 …F                                 VCP                                                   SHA
                               CPH
                                             Charge                               VGLS
            47 nF                            Pump
                               CPL                                                                  GLA
                                                                                  LS

                                     VGLS                                                           SLA
                                             VGLS
                                             Linear                            Gate Driver
                                            Regulator
          30 mA               DVDD                                                                                     VM
                                             DVDD                                 VCP
          1 …F                               Linear
                              AGND                                                                  GHB
                                            Regulator                             HS
                                              Power
                              PGND                                                                  SHB
                         ENABLE                                                   VGLS
                                                                 Digital                            GLB
                                                                 Core             LS
                              INHA
                                                                                                    SLB
                              INLA                                             Gate Driver

                                                                                                                       VM
                              INHB                                                VCP
                                                 Control      Smart Gate
                                                 Inputs         Drive                               GHC
                              INLB                                                HS
                                                               Protection
                                                                                                    SHC
                              INHC
                                                                                  VGLS
                                                                                                    GLC
                              INLC                                                LS

                                                                                                    SLC
             VCC               SDI
                                                                               Gate Driver                   VCC
                                                  SPI
                   RPU
                              SDO                                                                                RPU
                                                                               Fault Output         nFAULT

                              SCLK


                              nSCS
                 VIN
                               VIN                                                                  CB
                                                                                                             0.1 µF
                                                                                                                      LOUT
                          nSHDN                            Buck Regulator                           SW                        600 mA
          CIN
                                                           (LMR16006X)                                             DOUT
                              BGND                                                                  FB                            COUT
                                                                                                                       RFB1



                                                                                                                       RFB2



                                                                                              Copyright © 2017, Texas Instruments Incorporated

                                                  Figure 8-4. Block Diagram for DRV8320RS




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  VM
                                                                                                 VDRAIN                VM
                          VM
                                                                             VCP
                                                                                                 GHA
                         VCP                                                 HS
                1 …F
>10 …F 0.1 …F                            VCP                                                     SHA
                         CPH
                                        Charge                               VGLS
        47 nF                           Pump
                         CPL                                                                     GLA
                                                                             LS


                                VGLS
                                        VGLS                              Gate Driver
                                        Linear
                                       Regulator
                                                                                                                VM
        30 mA          DVDD                                                  VCP
                                        DVDD
        1 …F                            Linear                                                   GHB
                       AGND                                                  HS
                                       Regulator
                                         Power                                                   SHB
                       PGND
                                                                             VGLS
                                                              Digital                            GLB
                   ENABLE                                                    LS
                                                              Core

                        INHA
                                                                          Gate Driver

                         INLA                                                                             VM
                                                            Smart Gate       VCP
                                                              Drive                              GHC
                        INHB
                                                                             HS
                                                            Protection
                                                                                                 SHC
                         INLB
                                            Control                          VGLS
                                            Inputs
                                                                                                 GLC
                        INHC                                                 LS


                        INLC                                                                           VCC
                                                                          Gate Driver
                                                                                                   RPU
                       MODE
                                                                          Fault Output           nFAULT
                       IDRIVE
                         VDS
                        GAIN
             VCC
                                                                                                 SPC
                        VREF
                                                                                  AV             SNC         RSEN
    0.1 …F               SOC
                                                                                                 SPB
                         SOB                Output
                                            Offset                                AV             SNB                RSEN
                                             Bias
                         SOA
                                                                                                 SPA
                         CAL
                                                                                  AV             SNA                       RSEN




                                                  Figure 8-5. Block Diagram for DRV8323H




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     VM                                                                                                                   VM
                                                                                              VDRAIN
                            VM
                                                                               VCP
                                                                                              GHA
                            VCP                                                HS
                    1 …F
>10 …F 0.1 …F                              VCP                                                SHA
                            CPH
                                          Charge                               VGLS
                                          Pump
           47 nF
                            CPL                                                               GLA
                                                                               LS

                                  VGLS
                                          VGLS
                                          Linear                            Gate Driver
                                         Regulator
          30 mA            DVDD                                                                                   VM
                                          DVDD                                 VCP
          1 …F                            Linear                                              GHB
                           AGND                                                HS
                                         Regulator
                                           Power                                              SHB
                           PGND
                                                                               VGLS
                      ENABLE                                   Digital                        GLB
                                                               Core            LS

                           INHA
                                                                            Gate Driver
                           INLA
                                                                                                          VM
                                                             Smart Gate        VCP
                           INHB                                Drive                          GHC
                                              Control
                                              Inputs                           HS
                                                             Protection
                           INLB                                                               SHC
                                                                               VGLS
                           INHC                                                               GLC
                                                                               LS

                           INLC
                                                                                                      VCC
                                                                            Gate Driver
              VCC
                            SDI                                                                   RPU
          RPU                                  SPI
                                                                            Fault Output      nFAULT
                            SDO

                           SCLK


                           nSCS
              VCC
                                                                                              SPC
                           VREF                                                                              RSEN
                                                                                    AV        SNC
     0.1 …F                 SOC
                                                                                              SPB
                            SOB               Output
                                              Offset                                AV        SNB                    RSEN
                            SOA                Bias

                                                                                              SPA
                            CAL
                                                                                    AV        SNA                            RSEN




                                                                                             Copyright © 2017, Texas Instruments Incorporated

                                                   Figure 8-6. Block Diagram for DRV8323S




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www.ti.com                                                                                  SLVSDJ3D – FEBRUARY 2017 – REVISED MARCH 2022

   VM                                                                                                                           VM
                                                                                                    VDRAIN
                             VM
                                                                                VCP
                                                                                                    GHA
                            VCP                                                 HS
                    1 …F
>10 …F 0.1 …F                               VCP                                                     SHA
                            CPH
                                           Charge                               VGLS
          47 nF                            Pump
                            CPL                                                                     GLA
                                                                                LS


                                   VGLS
                                           VGLS                              Gate Driver
                           DGND            Linear
                                          Regulator
                                                                                                                        VM
                                                                                VCP
          30 mA            DVDD
                                           DVDD                                                     GHB
          1 …F                             Linear                               HS
                           AGND           Regulator
                                                                                                    SHB
                                            Power
                           PGND                                                 VGLS
                                                                Digital                             GLB
                                                                Core            LS
                      ENABLE

                                                                             Gate Driver
                           INHA
                                                                                                                 VM
                                                             Smart Gate         VCP
                            INLA                               Drive                                GHC
                                                                                HS
                                                              Protection
                           INHB                                                                     SHC
                                                                                VGLS
                            INLB
                                               Control                                              GLC
                                               Inputs                           LS

                           INHC
                                                                                                           VCC
                                                                             Gate Driver
                           INLC                                                                          RPU
                                                                             Fault Output           nFAULT
                           MODE
                       IDRIVE
                            VDS
                           GAIN
              VCC
                                                                                                    SPC
                           VREF
                                                                                     AV             SNC             RSEN
    0.1 …F                  SOC
                                                                                                    SPB
                            SOB                Output
                                               Offset                                AV             SNB                    RSEN
                                                Bias
                            SOA
                                                                                                    SPA
                            CAL
                                                                                     AV             SNA                             RSEN
              VIN

                            VIN                                                                     CB
                                                                                                               0.1 µF      LOUT      600 mA
                       nSHDN                              Buck Regulator                            SW
        CIN                                                                                                                  RFB1        COUT
                                                          (LMR16006X)                                           DOUT
                           BGND                                                                     FB
                                                                                                                             RFB2


                                                                                                  Copyright © 2017, Texas Instruments Incorporated

                                                 Figure 8-7. Block Diagram for DRV8323RH


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DRV8320, DRV8320R, DRV8323, DRV8323R
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     VM
                              VM                                                               VDRAIN                      VM
                                                                                VCP
                              VCP
                                                                                               GHA
                      1 …F                                                      HS
>10 …F 0.1 …F                                VCP
                              CPH
                                            Charge                                             SHA
           47 nF                            Pump                                VGLS
                              CPL
                                                                                               GLA
                                                                                LS
                                    VGLS
                             DGND           VGLS
                                            Linear                           Gate Driver
                                           Regulator
          30 mA              DVDD
                                                                                                                   VM
                                            DVDD                                VCP
          1 …F                              Linear
                             AGND
                                           Regulator                                           GHB
                                                                                HS
                                             Power
                             PGND
                                                                                               SHB
                                                                                VGLS
                        ENABLE
                                                                Digital                        GLB
                                                                Core            LS
                             INHA

                                                                             Gate Driver
                             INLA
                                                                                                            VM
                                                             Smart Gate         VCP
                             INHB               Control        Drive                           GHC
                                                Inputs                          HS
                                                              Protection
                             INLB
                                                                                               SHC
                                                                                VGLS
                             INHC
                                                                                               GLC
                                                                                LS
                             INLC
                                                                                                      VCC
              VCC                                                            Gate Driver
                              SDI                                                                 RPU
          RPU                                    SPI
                                                                             Fault Output      nFAULT
                              SDO
                             SCLK


                             nSCS
                VCC                                                                            SPC

                             VREF                                                    AV        SNC            RSEN

     0.1 …F                   SOC
                                                                                               SPB
                                                Output
                              SOB                                                    AV                               RSEN
                                                Offset                                         SNB
                                                 Bias
                              SOA
                                                                                               SPA
                              CAL                                                    AV        SNA                             RSEN
                VIN

                              VIN                                                              CB
                                                                                                        0.1 µF          LOUT    600 mA
                         nSHDN                            Buck Regulator                       SW
          CIN                                                                                                           RFB1          COUT
                                                          (LMR16006X)                                    DOUT
                             BGND                                                              FB
                                                                                                                        RFB2


                                                                                             Copyright © 2017, Texas Instruments Incorporated

                                                  Figure 8-8. Block Diagram for DRV8323RS


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8.3 Feature Description
Table 8-1 lists the recommended values of the external components for the gate driver and the buck regulator.
                                               Table 8-1. DRV832x External Components
      COMPONENTS                       PIN 1                    PIN 2                                RECOMMENDED
 GATE DRIVER AND SENSE AMPLIFIER
          CVM1                          VM                      PGND                      X5R or X7R, 0.1µF, VM-rated capacitor
          CVM2                          VM                      PGND                            ≥ 10µF, VM-rated capacitor
          CVCP                         VCP                       VM                           X5R or X7R, 25V, 1µF capacitor
           CSW                         CPH                       CPL                       X5R or X7R, 47nF, VM-rated capacitor
         CDVDD                        DVDD                      AGND                         X5R or X7R, 1µF, 6.3V capacitor
         RnFAULT                      VCC(1)                   nFAULT                                  Pullup resistor
          RSDO                        VCC(1)                     SDO                                   Pullup resistor
         RIDRIVE                      IDRIVE               AGND or DVDD                        DRV832x hardware interface
          RVDS                         VDS                 AGND or DVDD                        DRV832x hardware interface
         RMODE                        MODE                 AGND or DVDD                        DRV832x hardware interface
          RGAIN                        GAIN                AGND or DVDD                        DRV832x hardware interface
          CVREF                        VREF                AGND or DGND                  X5R or X7R, 0.1μF, VREF-rated capacitor
        RASENSE                         SPA                SNA and PGND                            Sense shunt resistor
        RBSENSE                        SPB                 SNB and PGND                            Sense shunt resistor
        RCSENSE                        SPC                 SNC and PGND                            Sense shunt resistor
 BUCK REGULATOR
           CVIN                         VIN                     BGND                    X5R or X7R, 1 to 10µF, VM-rated capacitor
         CBOOT                          SW                       CB                          X5R or X7R, 0.1µF, 16V capacitor
           DSW                          SW                      BGND                                  Schottky diode
           LSW                          SW                      OUT(2)                                Output inductor
          COUT                        OUT(2)                    BGND                         X5R or X7R, OUT rated capacitor
          RFB1                        OUT(2)                      FB
                                                                                         Resistor divider to set buck output voltage
          RFB2                          FB                      BGND

(1)    The VCC pin is not a pin on the DRV832x family of devices, but a VCC supply voltage pullup is required for the open-drain outputs,
       nFAULT and SDO. These pins can also be pulled up to DVDD.
(2)    The OUT pin is not a pin on the DRV8320R and DRV8323R devices, but is the regulated output voltage of the buck regulator after the
       output inductor.

8.3.1 Three Phase Smart Gate Drivers
The DRV832x family of devices integrates three, half-bridge gate drivers, each capable of driving high-side and
low-side N-channel power MOSFETs. A doubler charge pump provides the correct gate bias voltage to the
high-side MOSFETs across a wide operating voltage range in addition to providing 100% support of the duty
cycle. An internal linear regulator provides the gate bias voltage for the low-side MOSFETs. The half-bridge gate
drivers can be used in combination to drive a three-phase motor or separately to drive other types of loads.
The DRV832x family of devices implements a Smart Gate Drive architecture which allows the user to
dynamically adjust the gate drive current without requiring external resistors to limit the gate current. Additionally,
this architecture provides a variety of protection features for the external MOSFETs including automatic dead
time insertion, prevention of parasitic dV/dt gate turnon, and gate fault detection.
8.3.1.1 PWM Control Modes
The DRV832x family of devices provides four different PWM control modes to support various commutation
and control methods. Texas Instruments does not recommend changing the MODE pin or PWM_MODE register



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during operation of the power MOSFETs. Instead, set all INHx and INLx pins to logic low before changing the
MODE pin or PWM_MODE register.
8.3.1.1.1 6x PWM Mode (PWM_MODE = 00b or MODE Pin Tied to AGND)
In 6x PWM mode, each half-bridge supports three output states: low, high, or high-impedance (Hi-Z). The
corresponding INHx and INLx signals control the output state as listed in Table 8-2.
                                                 Table 8-2. 6x PWM Mode Truth Table
                                         INLx           INHx         GLx         GHx             SHx
                                          0               0           L           L              Hi-Z
                                          0               1           L           H               H
                                          1               0          H            L               L
                                          1               1           L           L              Hi-Z


8.3.1.1.2 3x PWM Mode (PWM_MODE = 01b or MODE Pin = 47kΩ to AGND)
In 3x PWM mode, the INHx pin controls each half-bridge and supports two output states: low or high. The INLx
pin is used to put the half bridge in the Hi-Z state. If the Hi-Z state is not required, tie all INLx pins to logic high.
The corresponding INHx and INLx signals control the output state as listed in Table 8-3.
                                                 Table 8-3. 3x PWM Mode Truth Table
                                         INLx           INHx         GLx         GHx             SHx
                                          0               X           L           L              Hi-Z
                                          1               0          H            L               L
                                          1               1           L           H               H


8.3.1.1.3 1x PWM Mode (PWM_MODE = 10b or MODE Pin = Hi-Z)
In 1x PWM mode, the DRV832x family of devices uses 6-step block commutation tables that are stored
internally. This feature allows for a three-phase BLDC motor to be controlled using one PWM sourced from
a simple controller. The PWM is applied on the INHA pin and determines the output frequency and duty cycle of
the half-bridges.
The half-bridge output states are managed by the INLA, INHB, and INLB pins which are used as state logic
inputs. The state inputs can be controlled by an external controller or connected directly to the digital outputs
of the Hall effect sensor from the motor (INLA = HALL_A, INHB = HALL_B, INLB = HALL_C). The 1x PWM
mode usually operates with synchronous rectification (low-side MOSFET recirculation); however, the mode
can be configured to use asynchronous rectification (MOSFET body diode freewheeling) on SPI devices. This
configuration is set using the 1PWM_COM bit in the SPI registers.
The INHC input controls the direction through the 6-step commutation table which is used to change the
direction of the motor when Hall effect sensors are directly controlling the state of the INLA, INHB, and INLB
inputs. Tie the INHC pin low if this feature is not required.
The INLC input brakes the motor by turning off all high-side MOSFETs and turning on all low-side MOSFETs
when the INLC pin is pulled low. This brake is independent of the state of the other input pins. Tie the INLC pin
high if this feature is not required.
                                                Table 8-4. Synchronous 1x PWM Mode
                      LOGIC AND HALL INPUTS                                                  GATE DRIVE OUTPUTS(1)
                     INHC = 0                    INHC = 1             PHASE A           PHASE B              PHASE C
  STATE                                                                                                                       DESCRIPTION
              INLA    INHB      INLB     INLA      INHB       INLB   GHA   GLA         GHB       GLB      GHC        GLC
     Stop       0       0        0        0         0          0      L     L           L         L         L         L            Stop
     Align      1       1        1        1         1          1     PWM   !PWM         L         H         L         H            Align
      1         1       1        0        0         0          1      L     L         PWM       !PWM        L         H           B→C
      2         1       0        0        0         1          1     PWM   !PWM         L         L         L         H           A→C
      3         1       0        1        0         1          0     PWM   !PWM         L         H         L         L            A→B

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                                           Table 8-4. Synchronous 1x PWM Mode (continued)
                       LOGIC AND HALL INPUTS                                                         GATE DRIVE OUTPUTS(1)
                      INHC = 0                        INHC = 1                 PHASE A          PHASE B                  PHASE C
  STATE                                                                                                                                    DESCRIPTION
               INLA     INHB     INLB        INLA      INHB        INLB       GHA      GLA     GHB       GLB            GHC       GLC
      4          0        0        1          1          1           0         L        L       L            H          PWM       !PWM          C→B
      5          0        1        1          1          0           0         L        H       L            L          PWM       !PWM          C→A
      6          0        1        0          1          0           1         L        H      PWM      !PWM             L         L            B→A

(1)       !PWM is the inverse of the PWM signal.

                              Table 8-5. Asynchronous 1x PWM Mode 1PWM_COM = 1 (SPI Only)
                       LOGIC AND HALL INPUTS                                                         GATE DRIVE OUTPUTS
                      INHC = 0                        INHC = 1                 PHASE A          PHASE B                  PHASE C
  STATE                                                                                                                                    DESCRIPTION
               INLA     INHB     INLB        INLA      INHB        INLB       GHA      GLA     GHB       GLB            GHC       GLC
   Stop          0        0        0          0          0           0         L        L       L            L           L         L             Stop
   Align         1        1        1          1          1           1        PWM       L       L            H           L         H             Align
      1          1        1        0          0          0           1         L        L      PWM           L           L         H            B→C
      2          1        0        0          0          1           1        PWM       L       L            L           L         H            A→C
      3          1        0        1          0          1           0        PWM       L       L            H           L         L            A→B
      4          0        0        1          1          1           0         L        L       L            H          PWM        L            C→B
      5          0        1        1          1          0           0         L        H       L            L          PWM        L            C→A
      6          0        1        0          1          0           1         L        H      PWM           L           L         L            B→A



Figure 8-9 and Figure 8-10 show the different possible configurations in 1x PWM mode.


                                    INHA                                                                         INHA
      MCU_PWM                                PWM                                    MCU_PWM                              PWM

                                    INLA                                                                         INLA                             H
      MCU_GPIO                               STATE0                                                                      STATE0
                                                                                                                 INHB
                                    INHB                                                                                 STATE1                       H
      MCU_GPIO                               STATE1                                                                                      BLDC Motor
                                                                 BLDC Motor                                      INLB
                                    INLB                                                                                 STATE2
      MCU_GPIO                               STATE2                                                                                                   H
                                                                                                                 INHC
                                    INHC                                            MCU_GPIO                             DIR
      MCU_GPIO                               DIR                                                                 INLC
                                                                                    MCU_GPIO                             nBRAKE
                                    INLC
      MCU_GPIO                               nBRAKE




            Figure 8-9. 1x PWM—Simple Controller                                       Figure 8-10. 1x PWM—Hall Effect Sensor

8.3.1.1.4 Independent PWM Mode (PWM_MODE = 11b or MODE Pin Tied to DVDD)
In independent PWM mode, the corresponding input pin independently controls each high-side and low-side
gate driver. This control mode lets the DRV832x family of devices drive separate high-side and low-side loads
with each half-bridge. These types of loads include unidirectional brushed DC motors, solenoids, and low-side
and high-side switches. In this mode, if the system is configured in a half-bridge configuration, turning on both
the high-side and low-side MOSFETs at the same time causes shoot-through.
                                            Table 8-6. Independent PWM Mode Truth Table
                                              INLx                 INHx               GLx              GHx
                                                  0                  0                  L                L
                                                  0                  1                  L                H
                                                  1                  0                 H                 L
                                                  1                  1                 H                 H


Because the high-side and low-side VDS overcurrent monitors share the SHx sense line, using the monitors
when both the high-side and low-side gate drivers of one half-bridge are split and being used is not possible.


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In this case, connect the SHx pin to the high-side driver and disable the VDS overcurrent monitors as shown in
Figure 8-11.

                                                        Disable
                                                                        +
                                                                  VDS
                                                                        ±
                                                                                                       VM
                                                                            VDRAIN

                                                    VCP
                                                                            GHx                                   Load
                               INHx                 HS

                                                                            SHx
                                                    VGLS
                               INLx
                                                                            GLx
                                                    LS

                                                                                            Load

                                                 Gate Driver                SLx/SPx


                                                        Disable
                                                                        +
                                                                  VDS
                                                                        ±



                          Figure 8-11. Independent PWM High-Side and Low-Side Drivers

If the half-bridge is used to implement only a high-side or low-side driver, using the VDS overcurrent monitors
is still possible. Connect the SHx pin as shown in Figure 8-12 or Figure 8-13. The unused gate driver and the
corresponding input pin can stay disconnected.


                                         +                                                                             +
                                   VDS                                                                           VDS
                                         ±                                                                             ±
                                                                   VM                                                                      VM
                                                  VDRAIN                                                                      VDRAIN
                        VCP                                                                           VCP
                                                  GHx                                                                         GHx          Load
       INHx             HS                                                        INHx                HS

                                                  SHx                                                                         SHx
                       VGLS                                                                          VGLS
       INLx                                                                       INLx
                                                  GLx                                                                         GLx
                        LS                                         Load                               LS



                     Gate Driver                  SLx/SPx                                          Gate Driver                SLx/SPx


                                       +                                                                             +
                                   VDS ±                                                                         VDS ±



              Figure 8-12. One High-Side Driver                                          Figure 8-13. One Low-Side Driver

8.3.1.2 Device Interface Modes
The DRV832x family of devices supports two different interface modes (SPI and hardware) to let the end
application design for either flexibility or simplicity. The two interface modes share the same four pins, allowing
the different versions to be pin-to-pin compatible. This compatibility lets application designers evaluate with one
interface version and potentially switch to another with minimal modifications to their design.
8.3.1.2.1 Serial Peripheral Interface (SPI)
The SPI devices support a serial communication bus that lets an external controller send and receive data
with the DRV832x. This support lets the external controller configure device settings and read detailed fault


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information. The interface is a four wire interface using the SCLK, SDI, SDO, and nSCS pins which are
described as follows:
•    The SCLK pin is an input that accepts a clock signal to determine when data is captured and propagated on
     the SDI and SDO pins.
•    The SDI pin is the data input.
•    The SDO pin is the data output. The SDO pin uses an open-drain structure and requires an external pullup
     resistor.
•    The nSCS pin is the chip select input. A logic low signal on this pin enables SPI communication with the
     DRV832x.
For more information on the SPI, see Section 8.5.1.
8.3.1.2.2 Hardware Interface
Hardware interface devices convert the four SPI pins into four resistor-configurable inputs which are GAIN,
IDRIVE, MODE, and VDS. This conversion lets the application designer configure the most common device
settings by tying the pin logic high or logic low, or with a simple pullup or pulldown resistor. This removes the
requirement for an SPI bus from the external controller. General fault information can still be obtained through
the nFAULT pin.
•    The GAIN pin configures the gain of the current sense amplifier.
•    The IDRIVE pin configures the gate drive current strength.
•    The MODE pin configures the PWM control mode.
•    The VDS pin configures the voltage threshold of the VDS overcurrent monitors.
For more information on the hardware interface, see Section 8.3.3.

                                                                              DVDD           DVDD

                                                                           RGAIN
                           SCLK                      SPI                             GAIN                        Hardware
                                                  Interface                                                      Interface
                                                                                                        DVDD
                                                                              DVDD
                            SDI                                                     IDRIVE

                 VCC                                                                         DVDD

                     RPU
                           SDO                                                      MODE

                                                                                                        DVDD

                           nSCS                                                       VDS

                                                                           RVDS




                            Figure 8-14. SPI                                       Figure 8-15. Hardware Interface

8.3.1.3 Gate Driver Voltage Supplies
The voltage supply for the high-side gate driver is created using a doubler charge pump that operates from the
VM voltage supply input. The charge pump lets the gate driver correctly bias the high-side MOSFET gate with
respect to the source across a wide input supply voltage range. The charge pump is regulated to keep a fixed
output voltage of VVM + 11V and supports an average output current of 25mA. When VVM is less than 12V,
the charge pump operates in full doubler mode and generates VVCP = 2 × VVM – 1.5V when unloaded. The
charge pump is continuously monitored for undervoltage events to prevent under-driven MOSFET conditions.
The charge pump requires an X5R or X7R, 1µF, 25V ceramic capacitor between the VM and VCP pins to act
as the storage capacitor. Additionally, an X5R or X7R, 47nF, VM-rated ceramic capacitor is required between the
CPH and CPL pins to act as the flying capacitor.


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                                        VM

                                                 VM


                                             1 …F
                                                VCP




                                                CPH


                                                               VM
                                             47 nF                        Charge
                                                                          Pump
                                                                          Control
                                                 CPL




                                       Figure 8-16. Charge Pump Architecture

The voltage supply of the low-side gate driver is created using a linear regulator that operates from the VM
voltage supply input. The linear regulator lets the gate driver correctly bias the low-side MOSFET gate with
respect to ground. The linear regulator output is fixed at 11V and supports an output current of 25mA.
8.3.1.4 Smart Gate Drive Architecture
The DRV832x gate drivers use an adjustable, complimentary, push-pull topology for both the high-side and
low-side drivers. This topology allows for both a strong pullup and pulldown of the external MOSFET gates.
Additionally, the gate drivers use a Smart Gate Drive architecture to provide additional control of the external
power MOSFETs, additional steps to protect the MOSFETs, and optimal tradeoffs between efficiency and
robustness. This architecture is implemented through two components called IDRIVE and TDRIVE which are
described in Section 8.3.1.4.1 and Section 8.3.1.4.2. Figure 8-17 shows the high-level functional block diagram
of the gate driver.
The IDRIVE gate drive current and TDRIVE gate drive time should be initially selected based on the parameters
of the external power MOSFET used in the system and the desired rise and fall times (see Section 9).
The high-side gate driver also implements a Zener clamp diode to help protect the external MOSFET gate from
overvoltage conditions in the case of external short-circuit events on the MOSFET.




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                       INHx                                                   VCP
                                                                                                                       VM

                                        Control
                                        Inputs
                       INLx                                                                           GHx
                                                          Level
                                                         Shifters

                                                                                             480 k
                                                                                                      SHx


                                                                          +
                                                                    VGS
                                                                          –

                                                                              VGLS


                                         Digital
                                         Core
                                                          Level                                       GLx
                                                         Shifters

                                                                                     150 k

                                                                                                      SLx/SPx


                                                                          +
                                                                    VGS
                                                                          –                           PGND




                                                   Figure 8-17. Gate Driver Block Diagram

8.3.1.4.1 IDRIVE: MOSFET Slew-Rate Control
The IDRIVE component implements adjustable gate drive current to control the MOSFET VDS slew rates.
The MOSFET VDS slew rates are a critical factor for optimizing radiated emissions, energy, duration of diode
recovery spikes, dV/dt gate turnon resulting in shoot-through, and switching voltage transients related to
parasitics in the external half-bridge. The IDRIVE component operates on the principal that the MOSFET VDS
slew rates are predominately determined by the rate of gate charge (or gate current) delivered during the
MOSFET QGD or Miller charging region. By letting the gate driver adjust the gate current, the gate driver can
effectively control the slew rate of the external power MOSFETs.
The IDRIVE component lets the DRV832x family of devices dynamically switch between gate drive currents
either through a register setting on SPI devices or the IDRIVE pin on hardware interface devices. The SPI
devices provide 16 IDRIVE settings ranging from 10mA to 1A source and 20mA to 2A sink. Hardware interface
devices provide 7 IDRIVE settings within the same ranges. The setting of the gate drive current is delivered to
the gate during the turnon and turnoff of the external power MOSFET for the tDRIVE duration. After the MOSFET
turnon or turnoff, the gate driver switches to a smaller hold IHOLD current to improve the gate driver efficiency. For
additional details on the IDRIVE settings, see Section 8.6 for the SPI devices and Section 8.3.3 for the hardware
interface devices.
8.3.1.4.2 TDRIVE: MOSFET Gate Drive Control
The TDRIVE component is an integrated gate drive state machine that provides automatic dead time insertion
through handshaking between the high-side and low-side gate drivers, parasitic dV/dt gate turnon prevention,
and MOSFET gate fault detection.
The first component of the TDRIVE state machine is automatic dead time insertion. Dead time is the period
of time between the switching of the external high-side and low-side MOSFETs to make sure that they do not
cross conduct and cause shoot-through. The DRV832x family of devices uses VGS voltage monitors to measure
the MOSFET gate-to-source voltage and determine the correct time to switch instead of relying on a fixed time
value. This feature lets the dead time of the gate driver adjust for variation in the system such as temperature



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drift and variation in the MOSFET parameters. An additional digital dead time (tDEAD) can be inserted and is
adjustable through the registers on SPI devices.
The second component of the TDRIVE state machine is parasitic dV/dt gate turnon prevention. To implement
this component, the TDRIVE state machine enables a strong pulldown current (ISTRONG) on the opposite
MOSFET gate whenever a MOSFET is switching. The strong pulldown occurs for the TDRIVE duration. This
feature helps remove parasitic charge that couples into the MOSFET gate when the voltage half-bridge switch
mode slews rapidly.
The third component of the TDRIVE state machine implements a scheme for gate fault detection to detect
pin-to-pin solder defects, a MOSFET gate failure, or stuck-high or stuck-low voltage condition on a MOSFET
gate. This implementation occurs with a pair of VGS gate-to-source voltage monitors for each half-bridge gate
driver. When the gate driver receives a command to change the state of the half-bridge, it starts to monitor the
gate voltage of the external MOSFET. If the VGS voltage has not reached the correct threshold at the end of the
tDRIVE period, the gate driver reports a fault. To make sure that a false fault is not detected, a tDRIVE time should
be selected that is longer than the time required to charge or discharge the MOSFET gate. The tDRIVE time does
not increase the PWM time and will terminate if another PWM command is received while active. For additional
details on the TDRIVE settings, see the Section 8.6 section for SPI devices. The hardware interface devices
have a fixed tDRIVE of 4µs.
Figure 8-18 shows an example of the TDRIVE state machine in operation.


         VINHx



         VINLx

                                                                                        tDRIVE

         VGHx

                                       tDEAD                                             tDEAD

                 IHOLD     IDRIVE      IHOLD     ISTRONG               IHOLD
          IGHx
                                                                                                     IDRIVE        IHOLD

                                      tDRIVE

         VGLx

                                       tDEAD                                             tDEAD

                            IHOLD                                              IDRIVE    IHOLD     ISTRONG         IHOLD
          IGLx
                                                   IDRIVE      IHOLD



                                               Figure 8-18. TDRIVE State Machine

8.3.1.4.3 Propagation Delay
The propagation delay time (tpd) is measured as the time between an input logic edge to a detected output
change. This time has three parts consisting of the digital input deglitcher delay, the digital propagation delay,
and the delay through the analog gate drivers.
The input deglitcher prevents high-frequency noise on the input pins from affecting the output state of the gate
drivers. To support multiple control modes and dead time insertion, a small digital delay is added as the input
command propagates through the device. Lastly, the analog gate drivers have a small delay that contributes to
the overall propagation delay of the device.



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8.3.1.4.4 MOSFET VDS Monitors
The gate drivers implement adjustable VDS voltage monitors to detect overcurrent or short-circuit conditions on
the external power MOSFETs. When the monitored voltage is greater than the VDS trip point (VVDS_OCP) for
longer than the deglitch time (tOCP), an overcurrent condition is detected and action is taken according to the
device VDS fault mode.
The high-side VDS monitors measure the voltage between the VDRAIN and SHx pins. In devices with three
current sense amplifiers (DRV8323 and DRV8323R), the low-side VDS monitors measure the voltage between
the SHx and SPx pins. If the current sense amplifier is unused, tie the SP pins to the common ground point of
the external half-bridges. On device options without the current sense amplifiers (DRV8320 and DRV8320R) the
low-side VDS monitor measures between the SHx and SLx pins.
For the SPI devices, the reference point of the low-side VDS monitor can be changed between the SPx and SNx
pins if desired with the LS_REF register setting.
The VVDS_OCP threshold is programmable from 0.06V to 1.88V. For additional information on the VDS monitor
levels, see Section 8.6 for SPI devices and in Section 8.3.3 for hardware interface devices.

                                                            VM                                                                     VM
                                                  VDRAIN                                                               VDRAIN
                                  +                                                                +
                  +           VDS                                                  +           VDS
            VDS                   ±                                          VDS                   ±
                  ±   VVDS_OCP                                                     ±   VVDS_OCP
                                                  GHx                                                                  GHx


                                                  SHx                                                                  SHx
                                     +                                                                    +
                  +            VDS                                               +                  VDS
            VDS                      ±                                       VDS                          ±
                  ±   VVDS_OCP                    GLx                            ±     VVDS_OCP                        GLx


                                                  SLx                                                                  SPx

                                                                                                              0
                                                                                                                              RSENSE
                                                  PGND                                                        1        SNx
                                                                                        LS_REF
                                                                                       (SPI Only)                      PGND

  Figure 8-19. DRV8320 and DRV8320R VDS Monitors
                                                                     Figure 8-20. DRV8323 and DRV8323R VDS Monitors

8.3.1.4.5 VDRAIN Sense Pin
The DRV832x family of devices provides a separate sense pin for the common point of the high-side MOSFET
drain. This pin is called VDRAIN. This pin lets the sense line for the overcurrent monitors (VDRAIN) and the
power supply (VM) stay separate and prevent noise on the VDRAIN sense line. This separation also lets
implementation of a small filter on the gate driver supply (VM) or insertion of a boost converter to support lower
voltage operation if desired. Care must still be used when designing the filter or separate supply because VM
is still the reference point for the VCP charge pump that supplies the high-side gate drive voltage (VGSH). The
VM supply must not drift too far from the VDRAIN supply to avoid violating the VGS voltage specification of the
external power MOSFETs.
8.3.2 DVDD Linear Voltage Regulator
A 3.3V, 30mA linear regulator is integrated into the DRV832x family of devices and is available for use by
external circuitry. This regulator can provide the supply voltage for a low-power MCU or other circuitry supporting
low current. The output of the DVDD regulator should be bypassed near the DVDD pin with a X5R or X7R, 1µF,
6.3V ceramic capacitor routed directly back to the adjacent AGND ground pin.
The DVDD nominal, no-load output voltage is 3.3V. When the DVDD load current exceeds 30mA, the regulator
functions like a constant-current source. The output voltage drops significantly with a current load greater than
30mA.



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                                                      VM



                                   REF     +
                                           ±                         DVDD    3.3 V, 30 mA


                                                                              0.1 …F
                                                                     AGND




                                  Figure 8-21. DVDD Linear Regulator Block Diagram

Use Equation 1 to calculate the power dissipated in the device by the DVDD linear regulator.

         P = VVM − VDVDD × IDVDD                                                                                           (1)

For example, at a VVM of 24V, drawing 20mA out of DVDD results in a power dissipation as shown in Equation 2.

         P = 24 V − 3.3 V × 20 mA = 414 mW                                                                                 (2)
8.3.3 Pin Diagrams
Figure 8-22 shows the input structure for the logic level pins, INHx, INLx, CAL, ENABLE, nSCS, SCLK, and SDI.
The input can be driven with a voltage or external resistor.


                                                   DVDD

                          STATE     RESISTANCE                                                INPUT

                            VIH     Tied to DVDD                                            Logic High

                            VIL     Tied to AGND                                             Logic Low
                                                                   100 k




                                     Figure 8-22. Logic-Level Input Pin Structure




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Figure 8-23 shows the structure of the four level input pins, MODE and GAIN, on hardware interface devices.
The input can be set with an external resistor.

                                                                                                    MODE       GAIN

                                                                     DVDD
                     STATE      RESISTANCE         DVDD                                        Independent    40 V/V
                                                                                    +
                       VI4      Tied to DVDD
                                                                         50 k       ±
                               Hi-Z (>500 kŸ WR                                                    1x PWM      20V/V
                       VI3
                                    AGND)
                                                                                    +
                                  47 NŸ “5%                           84 k
                       VI2
                                   to AGND                                          ±
                                                                                                   3x PWM     10 V/V
                       VI1      Tied to AGND
                                                                                    +

                                                                                    ±
                                                                                                   6x PWM      5 V/V




                                              Figure 8-23. Four Level Input Pin Structure

Figure 8-24 shows the structure of the seven level input pins, IDRIVE and VDS, on hardware interface devices.
The input can be set with an external resistor.

                                                                                                   IDRIVE      VDS



                                                                                                    1/2 A     Disabled
                                                                                    +

                                                                                    ±
                     STATE      RESISTANCE
                                                                                               570/1140 mA     1.88 V
                       VI7      Tied to DVDD                         DVDD           +
                                                    DVDD
                                                                                    ±
                                 18 k ± 5%
                       VI6
                                  to DVDD                                                      260/520 mA      1.13 V

                                 75 k ± 5%                               73 k       +
                       VI5
                                  to DVDD
                                                                                    ±
                                Hi-Z (>500 kŸ
                       VI4                                                                     120/240 mA      0.60 V
                                  to AGND)                            73 k
                                                                                    +
                                 75 k ± 5%
                       VI3
                                  to AGND                                           ±
                                  18 NŸ “5%                                                     60/120 mA      0.26 V
                       VI2
                                   to AGND
                                                                                    +

                       VI1      Tied to AGND                                        ±
                                                                                                   30/60 mA    0.13 V
                                                                                    +

                                                                                    ±
                                                                                                   10/20 mA    0.06 V




                                              Figure 8-24. Seven Level Input Pin Structure

Figure 8-25 shows the structure of the open-drain output pins, nFAULT and SDO. The open-drain output
requires an external pullup resistor to function correctly.


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                                                           DVDD


                                 STATE        STATUS     RPU

                                 No Fault     Inactive                                 OUTPUT

                                  Fault        Active                                    Active

                                                                                        Inactive


                                          Figure 8-25. Open-Drain Output Pin Structure

8.3.4 Low-Side Current Sense Amplifiers (DRV8323 and DRV8323R Only)
The DRV8323 and DRV8323R integrate three, high-performance low-side current sense amplifiers for current
measurements using low-side shunt resistors in the external half-bridges. Low-side current measurements are
commonly used to implement overcurrent protection, external torque control, or brushless DC commutation with
the external controller. All three amplifiers can be used to sense the current in each of the half-bridge legs or
one amplifier can be used to sense the sum of the half-bridge legs. The current sense amplifiers include features
such as programmable gain, offset calibration, unidirectional and bidirectional support, and a voltage reference
pin (VREF). If any of the three current sense amplifiers are not being used, they can be tied off by shorting the
o connect the SPx or SNx pin to the SNx pin to the SPx pin and leaving the SOx pin unconnected. Remember t
low-side FET source, so that the overcurrent VDS monitor is still functional.
8.3.4.1 Bidirectional Current Sense Operation
The SOx pin on the DRV8323 and DRV8323R outputs an analog voltage equal to the voltage across the SPx
and SNx pins multiplied by the gain setting (GCSA). The gain setting is adjustable between four different levels
(5V/V, 10V/V, 20V/V, and 40V/V). Use Equation 3 to calculate the current through the shunt resistor.

             VVREF
                   − VSOx
         I = G 2 ×R                                                                                                       (3)
              CSA   SENSE

                                                                  50k


                                                                  100k


                                                                  200k


                                                                  400k
                         SOx                                                                       I

                                                                          10k        SPx
                  VCC                                                –
                                                                          10k                         RSENSE
                        VREF                                         +
                                                                                      SNx
                        0.1 μF                                    50k

                                    ½            +                100k
                                                 –
                                                                  200k


                                                                  400k




                                 Figure 8-26. Bidirectional Current Sense Configuration




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                                                                         SO (V)


                                                                                                     VREF




                                                                                                     VVREF / 2
                                             VLINEAR




                                                                       SP ± SN (V)

                                          Figure 8-27. Bidirectional Current Sense Output
                                                                                           I

                                                                                      SP
                                                                  SO                            R
                                                                                 AV

                                                                                      SN

                                                              SO
                                                     VREF
                                                                                           SP ± SN
                                          VVREF ± 0.25 V                                               ±0.3 V

                                                                                                       ±I × R
                                                    VSO(range±)


                                              VSO(off)max
                                                                        VOFF,
                                                  VVREF / 2                                            0V
                                                                        VDRIFT
                                              VSO(off)min


                                                    VSO(range+)
                                                                                                       I×R

                                                     0.25 V                                            0.3 V

                                                        0V

                                         Figure 8-28. Bidirectional Current Sense Regions




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8.3.4.2 Unidirectional Current Sense Operation (SPI only)
On the DRV8323 and DRV8323R SPI devices, use the VREF_DIV bit to remove the VREF divider. In this case
the current sense amplifier operates unidirectionally and the SOx pin outputs an analog voltage equal to the
voltage across the SPx and SNx pins multiplied by the gain setting (GCSA). Use Equation 4 to calculate the
current through the shunt resistor.

             V     − 0.3 − VSOx
         7I = VREF
               GCSA × RSENSE                                                                                               (4)

                                                                  50k


                                                                 100k


                                                                 200k


                                                                 400k
                         SOx                                                                    I

                                                                           10k         SPx
                                                                    –
                                                                           10k                          RSENSE
                                                                    +
                  VCC                                                                  SNx
                                                                  50k
                        VREF
                                              +                  100k
                        0.1 μF
                                              –
                                                                 200k


                                                                 400k




                                 Figure 8-29. Unidirectional Current-Sense Configuration
                                     SO (V)


                                                                                                 VREF




                                                                                                 VVREF ± 0.3 V



                                                                                  VLINEAR




                                                                    SP ± SN (V)

                                    Figure 8-30. Unidirectional Current-Sense Output




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                                                                                            I

                                                                                       SP
                                                                    SO                           R
                                                                                  AV

                                                                                       SN

                                                                SO
                                                       VREF

                                           VVREF ± 0.25 V

                                              VSO(off)max
                                                                         VOFF,              SP ± SN
                                            VVREF ± 0.3 V                                             0V
                                                                         VDRIFT
                                                  VSO(off)min




                                                       VSO(range)
                                                                                                      I×R

                                                                                                      0.3 V

                                                       0.25 V

                                                         0V

                                        Figure 8-31. Unidirectional Current-Sense Regions

8.3.4.3 Auto Offset Calibration
To minimize DC offset, the DRV8323 and DRV8323R devices can perform an automatic offset calibration
through the SPI registers (CSA_CAL_X) or CAL pin. When the calibration is enabled, the inputs to the amplifier
are shorted, the load is disconnected, and the gain (GCSA) of the amplifier is changed to the 40V/V setting. The
amplifier then goes through an automatic trim routine to minimize the input offset. The automatic trim routine
requires 100µs to complete after the calibration is enabled. After this time, the inputs of the amplifier stay
shorted, the load stays disconnected, and the gain stays at 40V/V if further offset calibration is desired to be
done by the external controller. To complete the offset calibration, the CSA_CAL_X registers or CAL pin should
be taken back low. The gain is returned to the original gain setting after the device completes calibration. For the
best results, perform offset calibration when the external MOSFETS are not switching to decrease the potential
noise impact to the amplifier. When the current sense amplifiers go into a calibration mode, the VREF pin is set
to bidirectional mode if the device is configured in unidirectional mode. The setting of the VREF pin affects the
channels all three current sense amplifier, even if the CSA_CAL_X register is not set for the all channels.
8.3.4.4 MOSFET VDS Sense Mode (SPI Only)
The current sense amplifiers on the DRV8323 and DRV8323R SPI devices can be configured to amplify the
voltage across the external low-side MOSFET VDS. This configuration lets the external controller measure the
voltage drop across the MOSFET RDS(on) without the shunt resistor and then calculate the half-bridge current
level.
To enable this mode set the CSA_FET bit to 1. The positive input of the amplifier is then internally connected to
the SHx pin with an internal clamp to prevent high voltage on the SHx pin from damaging the sense amplifier
inputs. During this mode of operation, the SPx pins should stay disconnected. When the CSA_FET bit is set to 1,
the negative reference for the low-side VDS monitor is automatically set to the SNx pin, regardless of the state of
the LS_REF bit. This setting is implemented to prevent disabling of the low-side VDS monitor.
If the system operates in MOSFET VDS current sense mode, route the SHx and SNx pins with Kelvin
connections across the drain and source of the external low-side MOSFETs.




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                                                                 VM                                                                   VM

             High-Side                                  VDRAIN                                                               VDRAIN
                                                                                   High-Side
            VDS Monitor                                                           VDS Monitor
                        +                                                                    +
                  VDS                                                                  VDS
                        ±                                                                    ±
                                                        GHx                                                                  GHx


             (SPI only)                                                           (SPI only)

           CSA_FET = 0                                                           CSA_FET = 1
                                                        SHx                                                                  SHx

            LS_REF = 0                                                           LS_REF = X


             Low-Side                                                             Low-Side
            VDS Monitor                                                          VDS Monitor

                        +                                                                    +
                  VDS                                   GLx                            VDS                                   GLx
                        ±                                                                    ±
                              0                                                                    0
                              1                                                                    1

                            10 k                                                                 10 k
                                   10 k                 SPx                                             10 k                 SPx
     SOx                                                                  SOx
                     AV                                 RSENSE                            AV
                                   10 k                                                                 10 k                 SNx
                                                        SNx



                                                                                                                             GND
                                                        GND




      Figure 8-32. Resistor Sense Configuration                                 Figure 8-33. VDS Current Sense Mode


When operating in MOSFET VDS current sense mode, the amplifier is enabled at the end of the tDRIVE time.
At this time, the amplifier input is connected to the SHx pin, and the SOx output is valid. When the low-side
MOSFET receives a signal to turn off the amplifier inputs, SPx and SNx, are shorted together internally.
8.3.5 Step-Down Buck Regulator
The DRV8320R and DRV8323R have an integrated buck regulator (LMR16006) to supply power for an external
controller or system voltage rail. The LMR16006 device is a 60V, 600mA, buck (step-down) regulator.
The buck regulator has a very-low quiescent current during light loads to prolong battery life. The LMR16006
device improves performance during line and load transients by implementing a constant-frequency current-
mode control scheme which requires less output capacitance and simplifies frequency compensation design.
The LMR16006 is the LMR16006X device version that uses a 0.7MHz switching frequency.
The LMR16006 device decreases the external component count by integrating the bootstrap recharge diode.
The bias voltage for the integrated high-side MOSFET is supplied by a capacitor on the CB to SW pin. The
bootstrap capacitor voltage is monitored by a UVLO circuit and turns off the high-side MOSFET when the boot
voltage falls lower than a preset threshold.
The LMR16006 device can operate at high duty cycles because of the boot UVLO and then refreshes the wimp
MOSFET. The output voltage can be stepped down to as low as the 0.8V reference. The internal soft-start
feature minimizes inrush currents.
For additional details, a block diagram showing the wimp MOSFET, and design information refer to the
LMR16006 SIMPLE SWITCHER® 60 V 0.6 A Buck Regulators With High Efficiency Eco-mode datasheet.
8.3.5.1 Fixed Frequency PWM Control
The LMR16006 device has a fixed switching frequency and implements peak current-mode control. The output
voltage is compared through external resistors on the FB pin to an internal voltage reference by an error

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amplifier which drives the internal COMP node. An internal oscillator initiates the turnon of the high-side power
switch. The error amplifier output is compared to the high-side power switch current. When the power switch
current reaches the level set by the internal COMP voltage, the power switch turns off. The internal COMP
node voltage increases and decreases as the output current increases and decreases. The device implements a
current limit by clamping the COMP node voltage to a maximum level.
8.3.5.2 Bootstrap Voltage (CB)
The LMR16006 device has an integrated bootstrap regulator, and requires a small ceramic capacitor between
the CB and SW pins to provide the gate drive voltage for the high-side MOSFET. The CB capacitor is refreshed
when the high-side MOSFET is off and the low-side diode conducts. To improve dropout, the LMR16006 device
is designed to operate at 100% duty cycle as long as the CB to SW pin voltage is greater than 3V. When the
voltage from the CB to SW pin drops to less than 3V, the high-side MOSFET turns off using a UVLO circuit which
lets the low-side diode conduct and refresh the charge on the CB capacitor. Because the supply current sourced
from the CB capacitor is low, the high-side MOSFET can stay on for more switching cycles than are required
to refresh the capacitor. Therefore, the effective duty cycle of the switching regulator is high. Attention must be
given in maximum duty-cycle applications with a light load. To make sure the SW pin can be pulled to ground
to refresh the CB capacitor, an internal circuit charges the CB capacitor when the load is light or the device is
working in dropout condition.
8.3.5.3 Output Voltage Setting
The output voltage is set using the feedback pin (FB) and a resistor divider connected to the output as shown
in Figure 9-1. The voltage of the feedback pin is 0.765V, so the ratio of the feedback resistors sets the output
voltage according to Equation 5.

           VO = 0.765 V × 1 + R1
                              R2                                                                                         (5)

Typically the starting value of R2 is from 1kΩ to 100kΩ. Use Equation 6 to calculate the value of R1.

                             VO
           R1 = R2 ×       0.765 V − 1                                                                                   (6)

8.3.5.4 Enable nSHDN and VIN Undervoltage Lockout
The nSHDN pin of the LMR16006 device is an input that is tolerant of high voltages with an internal pullup
circuit. The device can be enabled even if the nSHDN pin is floating. The regulator can also be turned on using
1.23V or higher logic signals. If the use of a higher voltage is desired because of system or other constraints, a
100kΩ or larger value resistor is recommended between the applied voltage and the nSHDN pin to help protect
the device. When the nSHDN pin is pulled down to 0V, the device turns off and goes to the lowest shutdown
current mode. In shutdown mode the supply current decreases to approximately 1µA. If the shutdown function is
unused, the nSHDN pin can be tied to the VIN pin with a 100kΩ resistor. The maximum voltage to the nSHDN
pin should not exceed 60V. The LMR16006 device has an internal UVLO circuit to shut down the output if the
input voltage falls lower than a UVLO threshold level that is internally fixed. Shutting down the output in this
way makes sure the regulator is not latched into an unknown state during low input voltage conditions. The
regulator powers up when the input voltage exceeds the voltage level. If the UVLO voltage must be higher, use
the nSHDN pin to adjust the system UVLO by using external resistors.
8.3.5.5 Current Limit
The LMR16006 device implements current-mode control which uses the internal COMP voltage to turn off the
high-side MOSFET on a cycle-by-cycle basis. Each cycle, the switch current and internal COMP voltage are
compared. When the peak switch current intersects the COMP voltage, the high-side switch turns off. During
overcurrent conditions that pull the output voltage low, the error amplifier responds by driving the COMP node
high, increasing the switch current. The error amplifier output is clamped internally causing it to function as a
switch current limit.




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8.3.5.6 Overvoltage Transient Protection
The LMR16006 device incorporates an overvoltage transient protection (OVTP) circuit to minimize voltage
overshoot when recovering from output fault conditions or strong unloaded transients on power supply designs
with low-value output capacitance. For example, when the power supply output is overloaded, the error amplifier
compares the actual output voltage to the internal reference voltage. If the voltage of the FB pin is lower than
the internal reference voltage for a considerable time, the output of the error amplifier responds by clamping the
error amplifier output to a high voltage, therefore requesting the maximum output current. When the condition
clears, the regulator output rises and the error amplifier output transitions to the steady-state duty cycle. In
some applications, the output voltage of the power supply can respond faster than the error amplifier output can
respond which can result in output overshoot. The OVTP feature minimizes the output overshoot when using a
low-value output capacitor by implementing a circuit to compare the FB pin voltage to the OVTP threshold which
is 108% of the internal voltage reference. If the FB pin voltage is greater than the OVTP threshold, the high-side
MOSFET is disabled preventing current from flowing to the output and minimizing output overshoot. When the
FB voltage drops lower than the OVTP threshold, the high-side MOSFET can turn on at the next clock cycle.
8.3.5.7 Thermal Shutdown
The device implements an internal thermal shutdown to help protect the device if the junction temperature
exceeds 170°C (typical). The thermal shutdown forces the device to stop switching when the junction
temperature exceeds the thermal trip threshold. When the junction temperature decreases to less than 160°C
(typical), the device reinitiates the power-up sequence.
8.3.6 Gate Driver Protective Circuits
The DRV832x family of devices is protected against VM undervoltage, charge pump undervoltage, MOSFET
VDS overcurrent, gate driver shorts, and overtemperature events.
                                                Table 8-7. Fault Action and Response (SPI Devices)
       FAULT                  CONDITION                 CONFIGURATION      REPORT    GATE DRIVER      LOGIC                  RECOVERY
 VM undervoltage                                                                                                              Automatic:
                             VVM < VUVLO                      —            nFAULT       Hi-Z         Disabled
     (UVLO)                                                                                                                  VVM > VUVLO
     Charge pump                                         DIS_CPUV = 0b     nFAULT       Hi-Z          Active
                                                                                                                              Automatic:
     undervoltage            VVCP < VCPUV
                                                         DIS_CPUV = 1b      None        Active        Active                 VVCP > VCPUV
       (CPUV)
                                                                                                                              Latched:
                                                       OCP_MODE = 00b      nFAULT       Hi-Z          Active
                                                                                                                        CLR_FLT, ENABLE Pulse

 VDS overcurrent                                                                                                                Retry:
                            VDS > VVDS_OCP             OCP_MODE = 01b      nFAULT       Hi-Z          Active
  (VDS_OCP)                                                                                                                     tRETRY
                                                       OCP_MODE = 10b      nFAULT       Active        Active                   No action
                                                        OCP_MODE = 11b      None        Active        Active                   No action
                                                                                                                              Latched:
                                                       OCP_MODE = 00b      nFAULT       Hi-Z          Active
                                                                                                                        CLR_FLT, ENABLE Pulse

        VSENSE                                                                                                                  Retry:
                                                       OCP_MODE = 01b      nFAULT       Hi-Z          Active
      overcurrent           VSP > VSEN_OCP                                                                                      tRETRY
     (SEN_OCP)                                         OCP_MODE = 10b      nFAULT       Active        Active                   No action
                                                       OCP_MODE = 11b or
                                                                            None        Active        Active                   No action
                                                         DIS_SEN = 1b
                                                                                                                              Latched:
 Gate driver fault                                       DIS_GDF = 0b      nFAULT       Hi-Z          Active
                     Gate voltage stuck after tDRIVE                                                                    CLR_FLT, ENABLE Pulse
     (GDF)
                                                         DIS_GDF = 1b       None        Active        Active                   No action
                                                         OTW_REP = 0b       None        Active        Active                   No action
 Thermal warning
                               TJ > TOTW                                                                                      Automatic:
     (OTW)                                               OTW_REP = 1b      nFAULT       Active        Active
                                                                                                                           TJ < TOTW – THYS
       Thermal
                                                                                                                               Automatic:
      shutdown                TJ > TOTSD                      —            nFAULT       Hi-Z          Active
                                                                                                                           TJ < TOTSD – THYS
       (OTSD)



8.3.6.1 VM Supply Undervoltage Lockout (UVLO)
If at any time the input supply voltage on the VM pin falls lower than the VUVLO threshold, all of the external
MOSFETs are disabled, the charge pump is disabled, and the nFAULT pin is driven low. The FAULT and
VM_UVLO bits are also latched high in the registers on SPI devices. Normal operation starts again (gate driver


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operation and the nFAULT pin is released) when the VM undervoltage condition clears. The VM_UVLO bit stays
set until cleared through the CLR_FLT bit or an ENABLE pin reset pulse (tRST).
8.3.6.2 VCP Charge Pump Undervoltage Lockout (CPUV)
If at any time the voltage on the VCP pin (charge pump) falls lower than the VCPUV threshold voltage of the
charge pump, all of the external MOSFETs are disabled and the nFAULT pin is driven low. The FAULT and
CPUV bits are also latched high in the registers on SPI devices. Normal operation starts again (gate driver
operation and the nFAULT pin is released) when the VCP undervoltage condition clears. The CPUV bit stays set
until cleared through the CLR_FLT bit or an ENABLE pin reset pulse (tRST). Setting the DIS_CPUV bit high on
the SPI devices disables this protection feature. On hardware interface devices, the CPUV protection is always
enabled.
8.3.6.3 MOSFET VDS Overcurrent Protection (VDS_OCP)
A MOSFET overcurrent event is sensed by monitoring the VDS voltage drop across the external MOSFET
RDS(on). If the voltage across an enabled MOSFET exceeds the VVDS_OCP threshold for longer than the tOCP_DEG
deglitch time, a VDS_OCP event is recognized and action is done according to the OCP_MODE bit. On
hardware interface devices, the VVDS_OCP threshold is set with the VDS pin, the tOCP_DEG is fixed at 4µs, and
the OCP_MODE bit is configured for 4ms automatic retry but can be disabled by tying the VDS pin to DVDD.
On SPI devices, the VVDS_OCP threshold is set through the VDS_LVL SPI register, the tOCP_DEG is set through
the OCP_DEG SPI register, and the OCP_MODE bit can operate in four different modes: VDS latched shutdown,
VDS automatic retry, VDS report only, and VDS disabled.
8.3.6.3.1 VDS Latched Shutdown (OCP_MODE = 00b)
After a VDS_OCP event in this mode, all external MOSFETs are disabled and the nFAULT pin is driven low.
When the external MOSFETs are disabled in this way, the driver automatically uses a lower setting for the gate
drive current instead of the programmed IDRIVE setting. This setting lets any large current that may be present
to be switched off slowly to minimize any inductive kickback caused by parasitic inductance in the system.
The FAULT, VDS_OCP, and corresponding MOSFET OCP bits are latched high in the SPI registers. Normal
operation starts again (gate driver operation and the nFAULT pin is released) when the VDS_OCP condition
clears and a clear faults command is issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST).
8.3.6.3.2 VDS Automatic Retry (OCP_MODE = 01b)
After a VDS_OCP event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven
low. When the external MOSFETs are disabled in this way, the driver automatically uses a lower setting for
the gate drive current instead of the programmed IDRIVE setting. This setting lets any large current that may
be present to be switched off slowly to minimize any inductive kickback caused by parasitic inductance in the
system. The FAULT, VDS_OCP, and corresponding MOSFET OCP bits are latched high in the SPI registers.
Normal operation starts again automatically (gate driver operation and the nFAULT pin is released) after the
tRETRY time elapses. The FAULT, VDS_OCP, and MOSFET OCP bits stay latched until the tRETRY period expires.
8.3.6.3.3 VDS Report Only (OCP_MODE = 10b)
No protective action occurs after a VDS_OCP event in this mode. The overcurrent event is reported by driving
the nFAULT pin low and latching the FAULT, VDS_OCP, and corresponding MOSFET OCP bits high in the SPI
registers. The gate drivers continue to operate as usual. The external controller must manage the overcurrent
condition by acting appropriately. The reporting clears (nFAULT pin is released) when the VDS_OCP condition
clears and a clear faults command is issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST).
8.3.6.3.4 VDS Disabled (OCP_MODE = 11b)
No action or reporting occurs after a VDS_OCP event in this mode.
8.3.6.4 VSENSE Overcurrent Protection (SEN_OCP)
Half-bridge overcurrent is also monitored by sensing the voltage drop across the external current sense resistor
with the SP pin. If at any time the voltage on the SP input of the CSA exceeds the VSEN_OCP threshold for
longer than the tOCP_DEG deglitch time, a SEN_OCP event is recognized and action is done according to the


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OCP_MODE bit. On hardware interface devices, the VSENSE threshold is fixed at 1V, tOCP_DEG is fixed at 4µs,
and the OCP_MODE for VSENSE is fixed for 4ms automatic retry. On SPI devices, the VSENSE threshold is set
through the SEN_LVL SPI register, the tOCP_DEG is set through the OCP_DEG SPI register, and the OCP_MODE
bit can operate in four different modes: VSENSE latched shutdown, VSENSE automatic retry, VSENSE report only,
and VSENSE disabled.
8.3.6.4.1 VSENSE Latched Shutdown (OCP_MODE = 00b)
After a SEN_OCP event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven low.
The FAULT and SEN_OCP bits are latched high in the SPI registers. Normal operation starts again (gate driver
operation and the nFAULT pin is released) when the SEN_OCP condition clears and a clear faults command is
issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST).
8.3.6.4.2 VSENSE Automatic Retry (OCP_MODE = 01b)
After a SEN_OCP event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven
low. The FAULT, SEN_OCP, and corresponding sense OCP bits are latched high in the SPI registers. Normal
operation starts again automatically (gate driver operation and the nFAULT pin is released) after the tRETRY time
elapses. The FAULT, SEN_OCP, and sense OCP bits stay latched until the tRETRY period expires.
8.3.6.4.3 VSENSE Report Only (OCP_MODE = 10b)
No protective action occurs after a SEN_OCP event in this mode. The overcurrent event is reported by driving
the nFAULT pin low and latching the FAULT and SEN_OCP bits high in the SPI registers. The gate drivers
continue to operate. The external controller manages the overcurrent condition by acting appropriately. The
reporting clears (nFAULT released) when the SEN_OCP condition clears and a clear faults command is issued
either through the CLR_FLT bit or an ENABLE reset pulse (tRST).
8.3.6.4.4 VSENSE Disabled (OCP_MODE = 11b or DIS_SEN = 1b)
No action occurs after a SEN_OCP event in this mode. The SEN_OCP bit can be disabled independently of the
VDS_OCP bit by using the DIS_SEN SPI register.
8.3.6.5 Gate Driver Fault (GDF)
The GHx and GLx pins are monitored such that if the voltage on the external MOSFET gate does not increase
or decrease after the tDRIVE time, a gate driver fault is detected. This fault may be encountered if the GHx or
GLx pins are shorted to the PGND, SHx, or VM pins. Additionally, a gate driver fault may be encountered if the
selected IDRIVE setting is not sufficient to turn on the external MOSFET within the tDRIVE period. After a gate
drive fault is detected, all external MOSFETs are disabled and the nFAULT pin driven low. In addition, the FAULT,
GDF, and corresponding VGS bits are latched high in the SPI registers. Normal operation starts again (gate
driver operation and the nFAULT pin is released) when the gate driver fault condition clears and a clear faults
command is issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST). On SPI devices, setting the
DIS_GDF bit high disables this protection feature.
Gate driver faults can indicate that the selected IDRIVE or tDRIVE settings are too low to slew the external
MOSFET in the desired time. Increasing either the IDRIVE or tDRIVE setting can resolve gate driver faults in these
cases. Alternatively, if a gate-to-source short occurs on the external MOSFET, a gate driver fault is reported
because of the MOSFET gate not turning on.
8.3.6.6 Thermal Warning (OTP) (SPI only)
If the die temperature exceeds the trip point of the thermal warning (TOTW), the OTW bit is set in the registers of
SPI devices. The device performs no additional action and continues to function. When the die temperature falls
lower than the hysteresis point of the thermal warning, the OTW bit clears automatically. The OTW bit can also
be configured to report on the nFAULT pin by setting the OTW_REP bit to 1 through the SPI registers.
8.3.6.7 Thermal Shutdown (OTSD)
If the die temperature exceeds the trip point of the thermal shutdown limit (TOTSD), all the external MOSFETs are
disabled, the charge pump is shut down, and the nFAULT pin is driven low. In addition, the FAULT and TSD bits
are latched high. Normal operation starts again (gate driver operation and the nFAULT pin is released) when the

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overtemperature condition clears. The TSD bit stays latched high indicating that a thermal event occurred until a
clear fault command is issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST). This protection
feature cannot be disabled.
8.4 Device Functional Modes
8.4.1 Gate Driver Functional Modes
8.4.1.1 Sleep Mode
The ENABLE pin manages the state of the DRV832x family of devices. When the ENABLE pin is low, the device
goes to a low-power sleep mode. In sleep mode, all gate drivers are disabled, sense amplifiers (if present) are
disabled, all external MOSFETs are disabled, the charge pump is disabled, the DVDD regulator is disabled,
and the SPI bus is disabled. The LMR16006X buck regulator (if present) is not controlled by the ENABLE pin
and can be operated independently of the gate driver. The tSLEEP time must elapse after a falling edge on the
ENABLE pin before the device goes to sleep mode.

                                                                           Note
       The INHx and INLx pins should be low before tRST (max 40μs) after ENABLE goes low to prevent the
       GHx and GLx outputs from entering into Hi-Z state while any of the gates are high.

Figure 8-34 shows the behavior of the device after ENABLE goes low when the INHx and INLx pins are low prior
to the time when the driver outputs ignore the inputs 50μs after ENABLE goes low. The GHx and GLx pins will
remain low as the device begins the process to enter sleep mode. Figure 8-35 shows the behavior of the device
if the input PWMs are not pulled low prior to the driver outputs ignoring the inputs. The GHx and GLx pins will
follow the inputs for 50μs after ENABLE goes low, then will become Hi-Z until nFAULT goes low up to 400μs
after ENABLE is low. To avoid this behavior, the INHx and INLx pins should be low before tRST (max 40μs) after
ENABLE goes low as shown in Figure 8-34 to avoid the GHx and GLx outputs going into Hi-Z state while any of
the gate outputs are high.

                                  Up to 400 s                                                              Up to 400 s
                                                                                                                                            Gate driver
                    50 s                                                                     50 s                                          shutoff



    ENABLE                                                                    ENABLE



    nFAULT                                                                        nFAULT



      INHx                                                                          INHx


      INLx                                                                          INLx
                 Follow PWM                                                                Follow PWM
                                    Ignore PWM inputs                                                        Ignore PWM inputs
                    inputs                                                                    inputs



      VGSH                                                                          VGSH                Gate driver outputs in Hi-Z state
                               Gate driver outputs in Hi-Z state


      VGSL                                                                          VGSL

                                                                    Time                                                                                  Time

  Figure 8-34. ENABLE Low Timing Diagram: Inputs                              Figure 8-35. ENABLE Low Timing Diagram: Inputs
           Low Before PWM Inputs Ignored                                      Continue to Toggle 50μs After ENABLE Goes Low


The device comes out of sleep mode automatically if the ENABLE pin is pulled high. The tWAKE time must elapse
before the device is ready for inputs.
In sleep mode and when VVM < VUVLO, all external MOSFETs are disabled. The high-side gate pins, GHx, are
pulled to the SHx pin by an internal pulldown resistor and the low-side gate pins, GLx, are pulled to the PGND
pin by an internal pulldown resistor.




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                                                         Note
       During power up and power down of the device through the ENABLE pin, the nFAULT pin is held low
       as the internal regulators enable or disable. After the regulators have enabled or disabled, the nFAULT
       pin is automatically released. The duration that the nFAULT pin is low does not exceed the tSLEEP or
       tWAKE time.

8.4.1.2 Operating Mode
When the ENABLE pin is high and the VVM voltage is greater than the VUVLO voltage, the device goes to
operating mode. The tWAKE time must elapse before the device is ready for inputs. In this mode the charge
pump, low-side gate regulator, DVDD regulator, and SPI bus are active.
8.4.1.3 Fault Reset (CLR_FLT or ENABLE Reset Pulse)
In the case of device latched faults, the DRV832x family of devices goes to a partial shutdown state to help
protect the external power MOSFETs and system.
When the fault condition clears, the device can go to the operating state again by either setting the CLR_FLT
SPI bit on SPI devices or issuing a reset pulse to the ENABLE pin on either interface variant. The ENABLE
reset pulse (tRST) consists of a high-to-low-to-high transition on the ENABLE pin. The low period of the sequence
should fall with the tRST time window or else the device will start the complete shutdown sequence. The reset
pulse has no effect on any of the regulators, device settings, or other functional blocks.
8.4.2 Buck Regulator Functional Modes
8.4.2.1 Continuous Conduction Mode (CCM)
The LMR16006 integrated buck regulator steps the input voltage down to a lower output voltage. In continuous
conduction mode (when the inductor current never reaches zero at CCM), the buck regulator operates in two
cycles. The power switch is connected between the VIN and SW pins. During the first cycle of operation, the
transistor is closed and the diode is reverse biased. Energy is collected in the inductor and the load current is
supplied by the COUT capacitor and the rising current through the inductor. During the second cycle of operation,
the transistor is open and the diode is forward biased because the inductor current cannot instantaneously
change direction. The energy stored in the inductor is transferred to the load and output capacitor. The ratio
of these two cycles determines the output voltage. Equation 7 and Equation 8 define the approximate output
voltage.

               V
          D= V O                                                                                                       (7)
               VIN

where
•    D is the duty cycle of the switch

          D′ = 1 − D                                                                                                   (8)

The value of D and D' is required for design calculations.
8.4.2.2 Eco-mode™ Control Scheme
The LMR16006 device operates with the Eco-mode control scheme at light-load currents to improve efficiency
by reducing switching and gate drive losses. The LMR16006 device is designed so that if the output voltage is
within regulation and the peak switch current at the end of any switching cycle is less than the sleep-current
threshold, IINDUCTOR ≤ 80mA, the device goes into Eco-mode. For Eco-mode operation, the LMR16006 device
senses peak current, not average or load current, so the load current when the device goes into Eco-mode is
dependent on the input voltage, the output voltage, and the value of the output inductor. When the load current
is low and the output voltage is within regulation, the device goes into Eco-mode and draws only 28µA input
quiescent current.



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8.5 Programming
This section applies only to the DRV832x SPI devices.
8.5.1 SPI Communication
8.5.1.1 SPI
On DRV832x SPI devices, a SPI bus is used to set device configurations, operating parameters, and read out
diagnostic information. The SPI operates in secondary mode and connects to a primary controller. The SPI input
data (SDI) word consists of a 16bit word, with a 5bit command and 11bits of data. The SPI output data (SDO)
word consists of 11bit register data. The first 5bits are don't care bits.
A valid frame must meet the following conditions:
• The SCLK pin should be low when the nSCS pin transitions from high to low and from low to high.
• The nSCS pin should be pulled high for at least 400ns between words.
• When the nSCS pin is pulled high, any signals at the SCLK and SDI pins are ignored and the SDO pin is
   placed in the Hi-Z state.
• Data is captured on the falling edge of the SCLK pin and data is propagated on the rising edge of the SCLK
   pin.
• The most significant bit (MSB) is shifted in and out first.
• A full 16 SCLK cycles must occur for transaction to be valid.
• If the data word sent to the SDI pin is less than or more than 16 bits, a frame error occurs and the data word
   is ignored.
• For a write command, the existing data in the register being written to is shifted out on the SDO pin following
   the 5-bit command data.
The SPI registers are reset to the default settings on power up, when the device enters sleep mode, and when a
UVLO fault occurs.
8.5.1.1.1 SPI Format
The SDI input data word is 16 bits long and consists of the following format:
•    1 read or write bit, W (bit B15)
•    4 address bits, A (bits B14 through B11)
•    11 data bits, D (bits B10 through B0)
The SDO output data word is 16 bits long and the first 5 bits are don't care bits. The data word is the content of
the register being accessed.
For a write command (W0 = 0), the response word on the SDO pin is the data currently in the register being
written to.
For a read command (W0 = 1), the response word is the data currently in the register being read.
                                                   Table 8-8. SDI Input Data Word Format
    R/W                ADDRESS                                                      DATA
    B15     B14       B13      B12       B11        B10   B9     B8    B7     B6     B5     B4       B3     B2      B1        B0
    W0       A3        A2       A1       A0         D10   D9     D8    D7     D6     D5     D4       D3     D2      D1        D0

                                                  Table 8-9. SDO Output Data Word Format
             DON'T CARE BITS                                                        DATA
    B15     B14       B13      B12       B11        B10   B9     B8    B7     B6     B5     B4       B3     B2      B1        B0
    X         X        X         X        X         D10   D9     D8    D7     D6     D5     D4       D3     D2      D1        D0




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             nSCS




             SCLK



              SDI         X         MSB                                         LSB                              X




              SDO         Z         MSB                                         LSB                               Z



            Capture
             Point



           Propagate
             Point


                                    Figure 8-36. SPI Secondary Timing Diagram




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8.6 Register Maps
This section applies only to the DRV832x SPI devices.

                                                                                                       Note
        Do not modify reserved registers or addresses not listed in the register map (Table 8-10). Writing to these registers may have unintended
        effects. For all reserved bits, the default value is 0. To help prevent erroneous SPI writes from the primary controller, set the LOCK bits to lock
        the SPI registers.

                                                                 Table 8-10. DRV832xS and DRV832xRS Register Map
       Name              10              9                8         7                 6                5             4          3           2                 1                 0      Type   Address
                                                                                            DRV8320S and DRV8320RS
    Fault Status 1     FAULT         VDS_OCP             GDF       UVLO              OTSD         VDS_HA         VDS_LA      VDS_HB      VDS_LB         VDS_HC                VDS_LC    R       0h
    VGS Status 2       SA_OC          SB_OC            SC_OC       OTW               CPUV         VGS_HA         VGS_LA      VGS_HB      VGS_LB         VGS_HC            VGS_LC        R       1h
    Driver Control    Reserved       DIS_CPUV          DIS_GDF   OTW_REP                  PWM_MODE              1PWM_COM    1PWM_DIR     COAST              BRAKE         CLR_FLT      RW       2h
    Gate Drive HS                      LOCK                                               IDRIVEP_HS                                            IDRIVEN_HS                             RW       3h
    Gate Drive LS       CBC                   TDRIVE                                      IDRIVEP_LS                                            IDRIVEN_LS                             RW       4h
    OCP Control        TRETRY                DEAD_TIME                   OCP_MODE                          OCP_DEG                                VDS_LVL                              RW       5h
      Reserved                                                                                    Reserved                                                                             RW       6h
      Reserved                                                                                    Reserved                                                                             RW       7h
                                                                                            DRV8323S and DRV8323RS
    Fault Status 1     FAULT         VDS_OCP             GDF       UVLO              OTSD         VDS_HA         VDS_LA      VDS_HB      VDS_LB         VDS_HC                VDS_LC    R       0h
    VGS Status 2       SA_OC          SB_OC            SC_OC       OTW               CPUV         VGS_HA         VGS_LA      VGS_HB      VGS_LB         VGS_HC            VGS_LC        R       1h
    Driver Control    Reserved       DIS_CPUV          DIS_GDF   OTW_REP                  PWM_MODE              1PWM_COM    1PWM_DIR     COAST              BRAKE         CLR_FLT      RW       2h
    Gate Drive HS                      LOCK                                               IDRIVEP_HS                                            IDRIVEN_HS                             RW       3h
    Gate Drive LS       CBC                   TDRIVE                                      IDRIVEP_LS                                            IDRIVEN_LS                             RW       4h
    OCP Control        TRETRY                DEAD_TIME                   OCP_MODE                          OCP_DEG                                VDS_LVL                              RW       5h
    CSA Control       CSA_FET        VREF_DIV          LS_REF             CSA_GAIN                DIS_SEN       CSA_CAL_A   CSA_CAL_B   CSA_CAL_C                   SEN_LVL            RW       6h
      Reserved                                                                                    Reserved                                                                             RW       7h




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8.6.1 Status Registers
The status registers are used for reporting warning and fault conditions. The status registers are read-only
registers
Complex bit access types are encoded to fit into small table cells. Table 8-11 shows the codes that are used for
access types in this section.
                                       Table 8-11. Status Registers Access Type Codes
                                  Access Type        Code            Description
                                  Read Type
                                  R                  R               Read
                                  Reset or Default Value
                                  -n                                 Value after reset or the default value


8.6.1.1 Fault Status Register 1 (address = 0x00)
The fault status register 1 is shown in Figure 8-37 and described in Table 8-12.
Register access type: Read only
                                                 Figure 8-37. Fault Status Register 1
      10             9      8              7               6             5            4            3                2             1            0
     FAULT    VDS_OCP      GDF            UVLO           OTSD        VDS_HA        VDS_LA       VDS_HB           VDS_LB       VDS_HC        VDS_LC
     R-0b        R-0b      R-0b           R-0b           R-0b          R-0b          R-0b         R-0b            R-0b          R-0b          R-0b


                                  Table 8-12. Fault Status Register 1 Field Descriptions
     Bit     Field                                  Type        Default        Description
      10     FAULT                                  R           0b             Logic OR of FAULT status registers. Mirrors nFAULT pin.
      9      VDS_OCP                                R           0b             Indicates VDS monitor overcurrent fault condition
      8      GDF                                    R           0b             Indicates gate drive fault condition
      7      UVLO                                   R           0b             Indicates undervoltage lockout fault condition
      6      OTSD                                   R           0b             Indicates overtemperature shutdown
      5      VDS_HA                                 R           0b             Indicates VDS overcurrent fault on the A high-side MOSFET
      4      VDS_LA                                 R           0b             Indicates VDS overcurrent fault on the A low-side MOSFET
      3      VDS_HB                                 R           0b             Indicates VDS overcurrent fault on the B high-side MOSFET
      2      VDS_LB                                 R           0b             Indicates VDS overcurrent fault on the B low-side MOSFET
      1      VDS_HC                                 R           0b             Indicates VDS overcurrent fault on the C high-side MOSFET
      0      VDS_LC                                 R           0b             Indicates VDS overcurrent fault on the C low-side MOSFET




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8.6.1.2 Fault Status Register 2 (address = 0x01)
The fault status register 2 is shown in Figure 8-38 and described in Table 8-13.
Register access type: Read only
                                                         Figure 8-38. Fault Status Register 2
      10              9           8                7               6          5            4            3            2           1            0
    SA_OC         SB_OC         SC_OC         OTW               CPUV        VGS_HA       VGS_LA      VGS_HB       VGS_LB      VGS_HC        VGS_LC
     R-0b          R-0b          R-0b             R-0b          R-0b         R-0b         R-0b         R-0b        R-0b         R-0b         R-0b


                                        Table 8-13. Fault Status Register 2 Field Descriptions
     Bit      Field                                         Type       Default       Description
      10      SA_OC                                         R          0b            Indicates overcurrent on phase A sense amplifier (DRV8323xS)
      9       SB_OC                                         R          0b            Indicates overcurrent on phase B sense amplifier (DRV8323xS)
      8       SC_OC                                         R          0b            Indicates overcurrent on phase C sense amplifier (DRV8323xS)
      7       OTW                                           R          0b            Indicates overtemperature warning
      6       CPUV                                          R          0b            Indicates charge pump undervoltage fault condition
      5       VGS_HA                                        R          0b            Indicates gate drive fault on the A high-side MOSFET
      4       VGS_LA                                        R          0b            Indicates gate drive fault on the A low-side MOSFET
      3       VGS_HB                                        R          0b            Indicates gate drive fault on the B high-side MOSFET
      2       VGS_LB                                        R          0b            Indicates gate drive fault on the B low-side MOSFET
      1       VGS_HC                                        R          0b            Indicates gate drive fault on the C high-side MOSFET
      0       VGS_LC                                        R          0b            Indicates gate drive fault on the C low-side MOSFET




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8.6.2 Control Registers
The control registers are used to configure the device. The control registers are read and write capable.
Complex bit access types are encoded to fit into small table cells. Table 8-14 shows the codes that are used for
access types in this section.
                                      Table 8-14. Control Registers Access Type Codes
                                     Access Type     Code             Description
                                     Read Type
                                     R               R                Read
                                     Write Type
                                     W               W                Write
                                     Reset or Default Value
                                     -n                               Value after reset or the default value


8.6.2.1 Driver Control Register (address = 0x02)
The driver control register is shown in Figure 8-39 and described in Table 8-15.
Register access type: Read/Write
                                                 Figure 8-39. Driver Control Register
       10               9     8              7             6              5            4             3              2             1            0
                    DIS      DIS           OTW                                       1PWM         1PWM                                        CLR
     Reserved                                                  PWM_MODE                                          COAST         BRAKE
                   _CPUV    _GDF           _REP                                      _COM          _DIR                                       _FLT
     R/W-0b        R/W-0b   R/W-0b        R/W-0b                R/W-00b              R/W-0b       R/W-0b         R/W-0b        R/W-0b        R/W-0b


                                          Table 8-15. Driver Control Field Descriptions
       Bit      Field                               Type         Default        Description
       10       Reserved                            R/W          0b             Reserved
        9       DIS_CPUV                            R/W          0b             0b = Charge pump UVLO fault is enabled
                                                                                1b = Charge pump UVLO fault is disabled
        8       DIS_GDF                             R/W          0b             0b = Gate drive fault is enabled
                                                                                1b = Gate drive fault is disabled
        7       OTW_REP                             R/W          0b             0b = OTW is not reported on nFAULT or the FAULT bit
                                                                                1b = OTW is reported on nFAULT and the FAULT bit
       6-5      PWM_MODE                            R/W          00b            00b = 6x PWM Mode
                                                                                01b = 3x PWM mode
                                                                                10b = 1x PWM mode
                                                                                11b = Independent PWM mode
        4       1PWM_COM                            R/W          0b             0b = 1x PWM mode uses synchronous rectification
                                                                                1b = 1x PWM mode uses asynchronous rectification (diode
                                                                                freewheeling)
        3       1PWM_DIR                            R/W          0b             In 1x PWM mode this bit is ORed with the INHC (DIR) input
        2       COAST                               R/W          0b             Write a 1 to this bit to put all MOSFETs in the Hi-Z state
        1       BRAKE                               R/W          0b             Write a 1 to this bit to turn on all three low-side MOSFETs in 1x
                                                                                PWM mode.
                                                                                This bit is ORed with the INLC (BRAKE) input.
        0       CLR_FLT                             R/W          0b             Write a 1 to this bit to clear latched fault bits.
                                                                                This bit automatically resets after being written.




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8.6.2.2 Gate Drive HS Register (address = 0x03)
The gate drive HS register is shown in Figure 8-40 and described in Table 8-16.
Register access type: Read/Write
                                                      Figure 8-40. Gate Drive HS Register
      10              9           8               7             6                5          4            3             2                1         0
                   LOCK                                             IDRIVEP_HS                                             IDRIVEN_HS
                 R/W-011b                                           R/W-1111b                                              R/W-1111b


                                            Table 8-16. Gate Drive HS Field Descriptions
     Bit      Field                                      Type          Default       Description
     10-8     LOCK                                       R/W           011b          Write 110b to lock the settings by ignoring further register writes
                                                                                     except to these bits and address 0x02 bits 0-2.
                                                                                     Writing any sequence other than 110b has no effect when
                                                                                     unlocked.
                                                                                     Write 011b to this register to unlock all registers.
                                                                                     Writing any sequence other than 011b has no effect when
                                                                                     locked.
     7-4      IDRIVEP_HS                                 R/W           1111b         0000b = 10mA
                                                                                     0001b = 30mA
                                                                                     0010b = 60mA
                                                                                     0011b = 80mA
                                                                                     0100b = 120mA
                                                                                     0101b = 140mA
                                                                                     0110b = 170mA
                                                                                     0111b = 190mA
                                                                                     1000b = 260mA
                                                                                     1001b = 330mA
                                                                                     1010b = 370mA
                                                                                     1011b = 440mA
                                                                                     1100b = 570mA
                                                                                     1101b = 680mA
                                                                                     1110b = 820mA
                                                                                     1111b = 1000mA
     3-0      IDRIVEN_HS                                 R/W           1111b         0000b = 20mA
                                                                                     0001b = 60mA
                                                                                     0010b = 120mA
                                                                                     0011b = 160mA
                                                                                     0100b = 240mA
                                                                                     0101b = 280mA
                                                                                     0110b = 340mA
                                                                                     0111b = 380mA
                                                                                     1000b = 520mA
                                                                                     1001b = 660mA
                                                                                     1010b = 740mA
                                                                                     1011b = 880mA
                                                                                     1100b = 1140mA
                                                                                     1101b = 1360mA
                                                                                     1110b = 1640mA
                                                                                     1111b = 2000mA




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8.6.2.3 Gate Drive LS Register (address = 0x04)
The gate drive LS register is shown in Figure 8-41 and described in Table 8-17.
Register access type: Read/Write
                                                   Figure 8-41. Gate Drive LS Register
       10             9             8          7             6                5         4           3              2                1         0
      CBC                 TDRIVE                                 IDRIVEP_LS                                            IDRIVEN_LS
     R/W-1b               R/W-11b                                R/W-1111b                                             R/W-1111b


                                        Table 8-17. Gate Drive LS Register Field Descriptions
      Bit     Field                                   Type          Default       Description
      10      CBC                                     R/W           1b            Cycle-by-cycle operation. In retry OCP_MODE, for both
                                                                                  VDS_OCP and SEN_OCP, the fault is automatically cleared
                                                                                  when a PWM input is given
      9-8     TDRIVE                                  R/W           11b           00b = 500ns peak gate-current drive time
                                                                                  01b = 1000ns peak gate-current drive time
                                                                                  10b = 2000ns peak gate-current drive time
                                                                                  11b = 4000ns peak gate-current drive time
      7-4     IDRIVEP_LS                              R/W           1111b         0000b = 10mA
                                                                                  0001b = 30mA
                                                                                  0010b = 60mA
                                                                                  0011b = 80mA
                                                                                  0100b = 120mA
                                                                                  0101b = 140mA
                                                                                  0110b = 170mA
                                                                                  0111b = 190mA
                                                                                  1000b = 260mA
                                                                                  1001b = 330mA
                                                                                  1010b = 370mA
                                                                                  1011b = 440mA
                                                                                  1100b = 570mA
                                                                                  1101b = 680mA
                                                                                  1110b = 820mA
                                                                                  1111b = 1000mA
      3-0     IDRIVEN_LS                              R/W           1111b         0000b = 20mA
                                                                                  0001b = 60mA
                                                                                  0010b = 120mA
                                                                                  0011b = 160mA
                                                                                  0100b = 240mA
                                                                                  0101b = 280mA
                                                                                  0110b = 340mA
                                                                                  0111b = 380mA
                                                                                  1000b = 520mA
                                                                                  1001b = 660mA
                                                                                  1010b = 740mA
                                                                                  1011b = 880mA
                                                                                  1100b = 1140mA
                                                                                  1101b = 1360mA
                                                                                  1110b = 1640mA
                                                                                  1111b = 2000mA




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8.6.2.4 OCP Control Register (address = 0x05)
The OCP control register is shown in Figure 8-42 and described in Table 8-18.
Register access type: Read/Write
                                                       Figure 8-42. OCP Control Register
      10              9               8           7              6           5             4          3            2               1          0
    TRETRY                DEAD_TIME                   OCP_MODE                   OCP_DEG                               VDS_LVL
    R/W-0b                 R/W-01b                     R/W-01b                   R/W-01b                               R/W-1001b


                                             Table 8-18. OCP Control Field Descriptions
     Bit      Field                                       Type       Default       Description
      10      TRETRY                                      R/W        0b            0b = VDS_OCP and SEN_OCP retry time is 4ms
                                                                                   1b = VDS_OCP and SEN_OCP retry time is 50µs
     9-8      DEAD_TIME                                   R/W        01b           00b = 50ns dead time
                                                                                   01b = 100ns dead time
                                                                                   10b = 200ns dead time
                                                                                   11b = 400ns dead time
     7-6      OCP_MODE                                    R/W        01b           00b = Overcurrent causes a latched fault
                                                                                   01b = Overcurrent causes an automatic retrying fault
                                                                                   10b = Overcurrent is report only but no action is taken
                                                                                   11b = Overcurrent is not reported and no action is taken
     5-4      OCP_DEG                                     R/W        01b           00b = Overcurrent deglitch time of 2µs
                                                                                   01b = Overcurrent deglitch time of 4µs
                                                                                   10b = Overcurrent deglitch time of 6µs
                                                                                   11b = Overcurrent deglitch time of 8µs
     3-0      VDS_LVL                                     R/W        1001b         0000b = 0.06V
                                                                                   0001b = 0.13V
                                                                                   0010b = 0.2V
                                                                                   0011b = 0.26V
                                                                                   0100b = 0.31V
                                                                                   0101b = 0.45V
                                                                                   0110b = 0.53V
                                                                                   0111b = 0.6V
                                                                                   1000b = 0.68V
                                                                                   1001b = 0.75V
                                                                                   1010b = 0.94V
                                                                                   1011b = 1.13V
                                                                                   1100b = 1.3V
                                                                                   1101b = 1.5V
                                                                                   1110b = 1.7V
                                                                                   1111b = 1.88V




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8.6.2.5 CSA Control Register (DRV8323x Only) (address = 0x06)
The CSA control register is shown in Figure 8-43 and described in Table 8-19.
Register access type: Read/Write
This register is only available with the DRV8323x family of devices.
                                            Figure 8-43. CSA Control Register
       10             9     8           7              6           5             4            3              2             1             0
     CSA         VREF      LS                CSA                  DIS          CSA          CSA            CSA                  SEN
     _FET        _DIV     _REF              _GAIN                _SEN         _CAL_A       _CAL_B         _CAL_C                _LVL
     R/W-0b      R/W-1b   R/W-0b            R/W-10b              R/W-0b       R/W-0b        R/W-0b        R/W-0b               R/W-11b


                                      Table 8-19. CSA Control Field Descriptions
      Bit     Field                             Type       Default        Description
      10      CSA_FET                           R/W        0b             0b = Current sense amplifier positive input is SPx
                                                                          1b = Current sense amplifier positive input is SHx (also
                                                                          automatically sets the LS_REF bit to 1)
       9      VREF_DIV                          R/W        1b             0b = Current sense amplifier reference voltage is VREF
                                                                          (unidirectional mode)
                                                                          1b = Current sense amplifier reference voltage is VREF
                                                                          divided by 2
       8      LS_REF                            R/W        0b             0b = VDS_OCP for the low-side MOSFET is measured
                                                                          across SHx to SPx
                                                                          1b = VDS_OCP for the low-side MOSFET is measured across
                                                                          SHx to SNx
      7-6     CSA_GAIN                          R/W        10b            00b = 5V/V current sense amplifier gain
                                                                          01b = 10V/V current sense amplifier gain
                                                                          10b = 20V/V current sense amplifier gain
                                                                          11b = 40V/V current sense amplifier gain
       5      DIS_SEN                           R/W        0b             0b = Sense overcurrent fault is enabled
                                                                          1b = Sense overcurrent fault is disabled
       4      CSA_CAL_A                         R/W        0b             0b = Normal current sense amplifier A operation
                                                                          1b = Short inputs to current sense amplifier A for offset
                                                                          calibration
       3      CSA_CAL_B                         R/W        0b             0b = Normal current sense amplifier B operation
                                                                          1b = Short inputs to current sense amplifier B for offset
                                                                          calibration
       2      CSA_CAL_C                         R/W        0b             0b = Normal current sense amplifier C operation
                                                                          1b = Short inputs to current sense amplifier C for offset
                                                                          calibration
      1-0     SEN_LVL                           R/W        11b            00b = Sense OCP 0.25V
                                                                          01b = Sense OCP 0.5V
                                                                          10b = Sense OCP 0.75V
                                                                          11b = Sense OCP 1V




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9 Application and Implementation
                                                                 Note
       Information in the following applications sections is not part of the TI component specification,
       and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
       determining suitability of components for their purposes, as well as validating and testing their design
       implementation to confirm system functionality.

9.1 Application Information
The DRV832x family of devices is primarily used in applications for three-phase brushless DC motor control. The
design procedures in Section 9.2 highlight how to use and configure the DRV832x family of devices.
9.2 Typical Application
9.2.1 Primary Application
The DRV8323R SPI device is used in this application example.




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            0.8 to 60 V, 600 mA              LOUT
      VCC
                                      COUT                VM




                                                                                               0.1 µF
                             CIN
                                          100 k




                                                 48

                                                              47

                                                                         46

                                                                                    45

                                                                                               44

                                                                                                          43

                                                                                                                      42

                                                                                                                                  41

                                                                                                                                              40

                                                                                                                                                          39

                                                                                                                                                                      38

                                                                                                                                                                                  37
                                                      nSHDN

                                                                   VIN

                                                                              NC

                                                                                         SW

                                                                                                    CB

                                                                                                               BGND

                                                                                                                           INLC

                                                                                                                                       INHC

                                                                                                                                                   INLB

                                                                                                                                                               INHB

                                                                                                                                                                           INLA

                                                                                                                                                                                       INHA
                 RFB1
                                      1                                                                                                                                                             36       3.3 V, 30 mA
                                            FB                                                                                                                                           DVDD
                                                                                                                                                                                                               1 µF
                                      2                                                                                                                                                             35
                 RFB2
                                            PGND                                                                                                                                         AGND
                                      3                                                                                                                                                             34
                                            CPL                                                                                                                                               CAL
                     47 nF            4                                                                                                                                                             33
                                            CPH                                                                                                                                    ENABLE
                VM                    5                                                                                                                                                             32
                                            VCP                                                                                                                                           nSCS
                     1 µF             6                                                                                                                                                             31            VCC
                                            VM                                                                                                                                            SCLK
                                                                                                                 GND
       0.1 µF                         7                                                                                                                                                             30
                                                                                                                (PAD)                                                                                                         VCC
                     VDRAIN                 VDRAIN                                                                                                                                            SDI                     10 k
                                      8                                                                                                                                                             29
                        GHA                 GHA                                                                                                                                               SDO                               10 k
                                      9                                                                                                                                                             28
                        SHA                 SHA                                                                                                                                        nFAULT
                                     10                                                                                                                                                             27                  VCC
                        GLA                 GLA                                                                                                                                          DGND
                                                                                                                                                                                                              1 µF
                                     11                                                                                                                                                             26
                        SPA                 SPA                                                                                                                                           VREF
                                     12                                                                                                                                                             25
                        SNA                 SNA                                                                                                                                               SOA
                                                                                                               GHC
                                                                                                    GHB




                                                                                                                                                                           SOC
                                                                                                                           SHC




                                                                                                                                                               SNC



                                                                                                                                                                                       SOB
                                                      SNB




                                                                                         SHB




                                                                                                                                       GLC

                                                                                                                                                   SPC
                                                                   SPB

                                                                              GLB
                                                 13

                                                              14

                                                                         15

                                                                                    16

                                                                                               17

                                                                                                          18

                                                                                                                      19

                                                                                                                                  20

                                                                                                                                              21

                                                                                                                                                          22

                                                                                                                                                                      23

                                                                                                                                                                                  24
                                                                                                               GHC
                                                                                                    GHB



                                                                                                                           SHC




                                                                                                                                                               SNC
                                                      SNB




                                                                                         SHB




                                                                                                                                       GLC

                                                                                                                                                   SPC
                                                                   SPB

                                                                              GLB




            VM                              VM                                                                             VM                                                                 VM                  VM

            +                                                                                                                                                                                                     +
                                                                                VDRAIN



                        GHA                                                         GHB                                                                        GHC


                        SHA                                                         SHB                                                                        SHC
                                                               A                                                                         B                                                               C


                        GLA                                                         GLB                                                                        GLC



                        SPA                                                         SPB                                                                        SPC

                                   RSENSE                                                          RSENSE                                                                     RSENSE
                        SNA                                                         SNB                                                                        SNC



                                                      Figure 9-1. Primary Application Schematic




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9.2.1.1 Design Requirements
Table 9-1 lists the example input parameters for the system design.
                                                    Table 9-1. Design Parameters
 EXAMPLE DESIGN PARAMETER                                            REFERENCE                         EXAMPLE VALUE
 Nominal supply voltage                                                                                        24V
                                                                         VVM
 Supply voltage range                                                                                       8V to 45V
 MOSFET part number                                                                                      CSD18536KCS
 MOSFET total gate charge                                                 Qg                       83nC (typical) at VVGS = 10V
 MOSFET gate to drain charge                                              Qgd                             14nC (typical)
 Target output rise time                                                   tr                             100 to 300ns
 Target output fall time                                                   tf                              50 to 150ns
 PWM Frequency                                                           ƒPWM                                45kHz
 Buck regulator output voltage                                           VVCC                                 3.3V
 Maximum motor current                                                    Imax                                100A
 ADC reference voltage                                                   VVREF                                3.3V
 Winding sense current range                                            ISENSE                            –40A to +40A
 Motor RMS current                                                       IRMS                                 28.3A
 Sense resistor power rating                                            PSENSE                                 2W
 System ambient temperature                                               TA                            –20°C to +105°C


9.2.1.2 Detailed Design Procedure
9.2.1.2.1 External MOSFET Support
The DRV832x MOSFET support is based on the capacity of the charge pump and PWM switching frequency of
the output. For a quick calculation of MOSFET driving capacity, use Equation 9 and Equation 10 for three phase
BLDC motor applications.

           Trapezoidal 120° Commutation: IVCP > Qg × fPWM                                                                    (9)

where
•    ƒPWM is the maximum desired PWM switching frequency.
•    IVCP is the charge pump capacity, which depends on the VM pin voltage.
•    The multiplier based on the commutation control method, may vary based on implementation.

           Sinusoidal 180° Commutation: IVCP > 3 × Qg × fPWM                                                               (10)

9.2.1.2.1.1 Example
If a system with a VVM voltage of 8V (IVCP = 15mA) uses a maximum PWM switching frequency of 45kHz,
then the charge pump can support MOSFETs using trapezoidal commutation with a Qg less than 333nC, and
MOSFETs using sinusoidal commutation with a Qg less than 111nC.
9.2.1.2.2 IDRIVE Configuration
The strength of the gate drive current, IDRIVE, is selected based on the gate-to-drain charge of the external
MOSFETs and the target rise and fall times at the outputs. If the IDRIVE selected is too low for a given MOSFET,
then the MOSFET may not turn on completely within the tDRIVE time and a gate drive fault may be asserted.
Additionally, slow rise and fall times result in higher switching power losses. If the IDRIVE selected is too high for
a given MOSFET/layout, the gate-to-source voltage may overshoot, undershoot, or ring excessively which could
violate the ABS MAX of the device and damage the driver or FET. TI recommends adjusting these values in the
system with the required external MOSFETs and motor to determine the best possible setting for any application.



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The IDRIVEP and IDRIVEN current for both the low-side and high-side MOSFETs are independently adjustable
on SPI devices through the SPI registers. On hardware interface devices, both source and sink settings are
selected at the same time on the IDRIVE pin.
For MOSFETs with a known gate-to-drain charge Qgd, desired rise time (tr), and a desired fall time (tf), use
Equation 11 and Equation 12 to calculate the value of IDRIVEP and IDRIVEN (respectively).

                    Qgd
         IDRIVEP > t                                                                                                  (11)
                    r

                    Qgd
         IDRIVEN > t                                                                                                  (12)
                     f

9.2.1.2.2.1 Example
Use Equation 13 and Equation 14 to calculate the value of IDRIVEP1 and IDRIVEP2 (respectively) for a gate-to-drain
charge of 14 nC and a rise time from 100 to 300ns.

                    14 nC
         IDRIVEP1 = 100 ns = 140 mA                                                                                   (13)

                    14 nC
         IDRIVEP2 = 300 ns = 47 mA                                                                                    (14)

Select a value for IDRIVEP that is between 47mA and 140mA. For this example, the value of IDRIVEP was selected
as 120mA source.
Use Equation 15 and Equation 16 to calculate the value of I DRIVEN1 and IDRIVEN2 (respectively) for a gate-to-drain
charge of 14nC and a fall time from 50 to 150ns.

         IDRIVEN1 = 14 nC
                    50 ns = 280 mA                                                                                    (15)

                    14 nC
         IDRIVEN2 = 150 ns = 93 mA                                                                                    (16)

Select a value for IDRIVEN that is between 93mA and 280mA. For this example, the value of IDRIVEN was selected
as 240mA sink.
9.2.1.2.3 VDS Overcurrent Monitor Configuration
The VDS monitors are configured based on the worst-case motor current and the RDS(on) of the external
MOSFETs as shown in Equation 17.

         VDS_OCP > Imax × RDS on max                                                                                  (17)

9.2.1.2.3.1 Example
The goal of this example is to set the VDS monitor to trip at a current greater than 100A. According to the
CSD18536KCS 60 V N-Channel NexFET™ Power MOSFET data sheet, the RDS(on) value is 1.8 times higher
at 175°C, and the maximum RDS(on) value at a VGS of 10V is 1.6mΩ. From these values, the approximate
worst-case value of RDS(on) is 1.8 × 1.6mΩ = 2.88mΩ.
Using Equation 17 with a value of 2.88mΩ for RDS(on) and a worst-case motor current of 100A, Equation 18
shows the calculated value of the VDS monitors.

         VDS_OCP > 100 A × 2.88 mΩ      VDS_OCP > 0.288 V                                                             (18)

For this example, the value of VDS_OCP was selected as 0.31V.
The SPI devices allow for adjustment of the deglitch time for the VDS overcurrent monitor. The deglitch time can
be set to 2µs, 4µs, 6µs, or 8µs.

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9.2.1.2.4 Sense Amplifier Bidirectional Configuration (DRV8323 and DRV8323R)
The sense amplifier gain on the DRV8323, DRV8323R devices and sense resistor value are selected based on
the target current range, VREF voltage supply, power rating of the sense resistor, and operating temperature
range. For bidirectional operation of the sense amplifier, the dynamic range at the output is approximately
calculated as shown in Equation 19.

                                V
           VO = VVREF − 0.25 V − VREF
                                  2                                                                                    (19)

Use Equation 20 to calculate the approximate value of the selected sense resistor with VO calculated using
Equation 19.

                   V
           R = A O× I PSENSE > IRMS2 × R                                                                               (20)
                  V

From Equation 19 and Equation 20, select a target gain setting based on the power rating of the target sense
resistor.
9.2.1.2.4.1 Example
In this system example, the value of the VREF voltage is 3.3V with a sense current from –40 to +40A. The linear
range of the SOx output is 0.25V to VVREF – 0.25V (from the VLINEAR specification). The differential range of the
sense amplifier input is –0.3 to +0.3V (VDIFF).

           VO = 3.3 V − 0.25 V − 3.32 V = 1.4 V                                                                        (21)

           R = A 1.4 V             2
                  × 40 A 2 W > 28.3 × R           R < 2.5 mΩ                                                           (22)
                  V

           2.5 mΩ > A 1.4 V
                       × 40 A         AV > 14                                                                          (23)
                         V

Therefore, the gain setting must be selected as 20V/V or 40V/V and the value of the sense resistor must be less
than 2.5mΩ to meet the power rating for the sense resistor. For this example, the gain setting was selected as
20V/V. The value of the resistor and worst case current can be verified that R < 2.5mΩ and Imax = 40A does not
violate the differential range specification of the current sense amplifier input (VSPxD).
9.2.1.2.5 Buck Regulator Configuration (DRV8320R and DRV8323R)
For a detailed design procedure and information on selecting the correct buck regulator external components,
refer to the LMR16006 SIMPLE SWITCHER® 60 V 0.6 A Buck Regulators With High Efficiency Eco-mode data
sheet.




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9.2.1.3 Application Curves




        Figure 9-2. Gate Drive at 20% Duty Cycle                    Figure 9-3. Gate Drive at 80% Duty Cycle




     Figure 9-4. BLDC Motor Commutation 1000 RPM               Figure 9-5. BLDC Motor Commutation 2000 RPM




      Figure 9-6. IDRIVE Maximum Setting Positive                Figure 9-7. IDRIVE Maximum Setting Negative
                         Current                                                    Current




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      Figure 9-8. IDRIVE Minimum Setting Positive                       Figure 9-9. IDRIVE Minimum Setting Negative
                        Current                                                            Current




  Figure 9-10. Current going out of SHx, IDRIVE_P =                  Figure 9-11. Current going into of SHx, IDRIVE_P =
            260mA and IDRIVE_N =520-mA                                         260mA and IDRIVE_N =520-mA

9.2.2 Alternative Application
In this application, one sense amplifier is used in unidirectional mode for a summing current sense scheme often
used in trapezoidal or hall-based BLDC commutation control.




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            0.8 to 60 V, 600 mA              LOUT
      VCC
                                      COUT                VM




                                                                                               0.1 µF
                             CIN
                                          100 k




                                                 48

                                                              47

                                                                         46

                                                                                    45

                                                                                               44

                                                                                                          43

                                                                                                                      42

                                                                                                                                  41

                                                                                                                                              40

                                                                                                                                                          39

                                                                                                                                                                      38

                                                                                                                                                                                  37
                                                      nSHDN

                                                                   VIN

                                                                              NC

                                                                                         SW

                                                                                                    CB

                                                                                                               BGND

                                                                                                                           INLC

                                                                                                                                       INHC

                                                                                                                                                   INLB

                                                                                                                                                               INHB

                                                                                                                                                                           INLA

                                                                                                                                                                                       INHA
                 RFB1
                                      1                                                                                                                                                             36       3.3 V, 30 mA
                                            FB                                                                                                                                           DVDD
                                                                                                                                                                                                               1 µF
                                      2                                                                                                                                                             35
                 RFB2
                                            PGND                                                                                                                                         AGND
                                      3                                                                                                                                                             34
                                            CPL                                                                                                                                               CAL
                     47 nF            4                                                                                                                                                             33
                                            CPH                                                                                                                                    ENABLE
                VM                    5                                                                                                                                                             32
                                            VCP                                                                                                                                           nSCS
                     1 µF             6                                                                                                                                                             31            VCC
                                            VM                                                                                                                                            SCLK
                                                                                                                 GND
       0.1 µF                         7                                                                                                                                                             30
                                                                                                                (PAD)                                                                                                         VCC
                     VDRAIN                 VDRAIN                                                                                                                                            SDI                     10 k
                                      8                                                                                                                                                             29
                        GHA                 GHA                                                                                                                                               SDO                               10 k
                                      9                                                                                                                                                             28
                        SHA                 SHA                                                                                                                                        nFAULT
                                     10                                                                                                                                                             27                  VCC
                        GLA                 GLA                                                                                                                                          DGND
                                                                                                                                                                                                              1 µF
                                     11                                                                                                                                                             26
                        SPA                 SPA                                                                                                                                           VREF
                                     12                                                                                                                                                             25
                        SNA                 SNA                                                                                                                                               SOA
                                                                                                               GHC
                                                                                                    GHB




                                                                                                                                                                           SOC
                                                                                                                           SHC




                                                                                                                                                               SNC



                                                                                                                                                                                       SOB
                                                      SNB




                                                                                         SHB




                                                                                                                                       GLC

                                                                                                                                                   SPC
                                                                   SPB

                                                                              GLB
                                                 13

                                                              14

                                                                         15

                                                                                    16

                                                                                               17

                                                                                                          18

                                                                                                                      19

                                                                                                                                  20

                                                                                                                                              21

                                                                                                                                                          22

                                                                                                                                                                      23

                                                                                                                                                                                  24
                                                                                                               GHC
                                                                                                    GHB



                                                                                                                           SHC
                                                                                         SHB




                                                                                                                                       GLC

                                                                                                                                                   SPC
                                                                   SPB

                                                                              GLB




            VM                              VM                                                                             VM                                                                 VM                  VM

            +                                                                                                                                                                                                     +
                                                                                VDRAIN



                        GHA                                                         GHB                                                                        GHC


                        SHA                                                         SHB                                                                        SHC
                                                               A                                                                         B                                                               C


                        GLA                                                         GLB                                                                        GLC



                        SPA                                                         SPB                                                                        SPC

                                   RSENSE
                        SNA



                                              Figure 9-12. Alternative Application Schematic

9.2.2.1 Design Requirements
Table 9-2 lists the example design input parameters for system design.




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                                                     Table 9-2. Design Parameters
 EXAMPLE DESIGN PARAMETER                                         REFERENCE                         EXAMPLE VALUE
 ADC reference voltage                                              VVREF                                 3.3V
 Sensed current                                                     ISENSE                               0 to 40A
 Motor RMS current                                                   IRMS                                 28.3A
 Sense-resistor power rating                                        PSENSE                                 3W
 System ambient temperature                                          TA                              –20°C to +105°C


9.2.2.2 Detailed Design Procedure
9.2.2.2.1 Sense Amplifier Unidirectional Configuration
The sense amplifiers are configured to be unidirectional through the registers on SPI devices by writing a 0 to
the VREF_DIV bit.
The sense amplifier gain and sense resistor values are selected based on the target current range, VREF, power
rating of the sense resistor, and operating temperature range. In unidirectional operation of the sense amplifier,
use Equation 24 to calculate the approximate value of the dynamic range at the output.

           VO = VVREF − 0.25 V − 0.25 V = VVREF − 0.5 V                                                                (24)

Use Equation 25 to calculate the approximate value of the selected sense resistor.

                   V
           R = A O× I PSENSE > IRMS2 × R                                                                               (25)
                  V

where
•    VO = VVREF − 0.5 V
From Equation 24 and Equation 25, select a target gain setting based on the power rating of a target sense
resistor.
9.2.2.2.1.1 Example
In this system example, the value of the VREF voltage is 3.3 V with a sense current from 0 to 40 A. The linear
range of the SOx output for the DRV8323x device is 0.25 V to VVREF – 0.25 V (from the VLINEAR specification).
The differential range of the sense-amplifier input is –0.3 to +0.3 V (VDIFF).

           VO = 3.3 V − 0.5 V = 2.8 V                                                                                  (26)

           R = A 2.8 V             2
                  × 40 A 3 W > 28.3 × R             R < 3.75 mΩ                                                        (27)
                  V

           3.75 mΩ > A 2.8 V
                        × 40 A          AV > 18.7                                                                      (28)
                           V

Therefore, the gain setting must be selected as 20 V/V or 40 V/V and the value of the sense resistor must
be less than 3.75 mΩ to meet the power rating for the sense resistor. For this example, the gain setting was
selected as 20 V/V. The value of the resistor and worst-case current can be verified that R < 3.75 mΩ and Imax =
40 A does not violate the differential range specification of the sense amplifier input (VSPxD).




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9.2.3 Unused Pins and Features
This section details the appropriate handling of unused pins and blocks of the device. If a feature such as the
CSA or Buck will not be used, check this section for guidance.
                                         Table 9-3. Unused Pins and Features
 Unused Feature                           Associated Pin(s)                      Recommendation
 Unused Half-Bridge                       GHx and GLx                            Float
                                          PWM Inputs                             Tie to GND or float
                                          SHx                                    Float
 Unused HS or LS (Individually)           SHx/INHx/INLx/GHx/GLx                  See Independent PWM Mode
 Unused CSA                               SPx and SNx                            Tie to GND
                                          SOx                                    Float
                                          VREF                                   Tie to
                                                                                 DVDD
 Unused Buck                              All Pins                               Tie to GND, remove all external components
 Unused SPI                               SDI/SDO/nSCS/SCLK                      Float




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10 Power Supply Recommendations
The DRV832x family of devices is designed to operate from an input voltage supply (VM) range from 6V to
60V. A 0.1µF ceramic capacitor rated for VM must be placed as close to the device as possible. In addition,
a bulk capacitor must be included on the VM pin but can be shared with the bulk bypass capacitance for the
external power MOSFETs. Additional bulk capacitance is required to bypass the external half-bridge MOSFETs
and should be sized according to the application requirements.
10.1 Power Supply Consideration in Generator Mode
When the motor shaft of BLDC or PMSM motor is turned by an external force, the motor windings will generate
a voltage on the motor inputs. This condition is known as generator mode or motor back-drive. In the generator
mode, a positive voltage can be observed on SHx pins of the device. If there is a switch between VDRAIN and
VM (SWVDRAIN in Figure 10-1 ) and the following conditions exist in the system, the absolute max voltage of VCP
with respect to VM needs to be reviewed;
• Generator mode
• SWVDRAIN is off
• VM and VCP are low voltage (e.g. VM = 0V)
If SHx voltage (VSHx) exceeds VCP voltage, the VCP voltage starts following VSHx because of the device internal
diodes D1 and D2 (or D3). If VCP - VM voltage exceeds the absolute max voltage of DRV832x, the ESD diode
D4 starts conducting and results in a big current from SHx to VM through the diodes D2, D1 and D4. To avoid
this condition, it is recommended to add an external diode DVDRAIN_VM between VDRAIN and VM.
                                                                                           SWVDRAIN

          VBAT
                                                                                Optional

                              VM                             VCP                            DVDRAN_VM

                                                                        DRV832x
                                                  ESD
                                                                                           VDRAIN
                                                       D4




                                                                   D1
                                                                                           GHx
                    INHx                          Level
                                                  shifter
                                                                   D2      D3                                                  external
                                                                                                                                force
                                                                                           SHx

                                                                                                 VSHx                    M
                                                            VGLS




                                                                                           GLx
                                                  Level
                     INLx
                                                  shifter

                                                                                           SLx

                                                                                                               GND


                                 Figure 10-1. Power Supply Consideration in Generator mode




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10.2 Bulk Capacitance Sizing
Having appropriate local bulk capacitance is an important factor in motor drive system design. It is generally
beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size. The
amount of local capacitance depends on a variety of factors including:
• The highest current required by the motor system
• The power supply's type, capacitance, and ability to source current
• The amount of parasitic inductance between the power supply and motor system
• The acceptable supply voltage ripple
• Type of motor (brushed DC, brushless DC, stepper)
• The motor startup and braking methods
The inductance between the power supply and motor drive system will limit the rate current can change from the
power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands
or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
remains stable and high current can be quickly supplied.
The data sheet provides a recommended minimum value, but system level testing is required to determine the
appropriate sized bulk capacitor.

                                          Parasitic Wire
                                           Inductance
                  Power Supply                                                 Motor Drive System


                                                                                                VM



                        +                                            +
                                                                                                       Motor Driver
                        ±


                                                                                              GND



                                                                  Local                IC Bypass
                                                              Bulk Capacitor           Capacitor



                                 Figure 10-2. Motor Drive Supply Parasitics Example




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11 Layout
11.1 Layout Guidelines
Bypass the VM pin to the PGND pin using a low-ESR ceramic bypass capacitor with a recommended value of
0.1µF. Place this capacitor as close to the VM pin as possible with a thick trace or ground plane connected to
the PGND pin. Additionally, bypass the VM pin using a bulk capacitor rated for VM. This component can be
electrolytic. This capacitance must be at least 10µF.
Additional bulk capacitance is required to bypass the high current path on the external MOSFETs. This bulk
capacitance should be placed such that it minimizes the length of any high current paths through the external
MOSFETs. The connecting metal traces should be as wide as possible, with numerous vias connecting PCB
layers. These practices minimize inductance and let the bulk capacitor deliver high current.
Place a low-ESR ceramic capacitor between the CPL and CPH pins. This capacitor should be 47nF, rated for
VM, and be of type X5R or X7R. Additionally, place a low-ESR ceramic capacitor between the VCP and VM pins.
This capacitor should be 1µF, rated for 25V, and be of type X5R or X7R.
Bypass the DVDD pin to the AGND pin with a 1µF low-ESR ceramic capacitor rated for 6.3V and of type X5R or
X7R. Place this capacitor as close to the pin as possible and minimize the path from the capacitor to the AGND
pin.
The VDRAIN pin can be shorted directly to the VM pin. However, if a significant distance is between the device
and the external MOSFETs, use a dedicated trace to connect to the common point of the drains of the high-side
external MOSFETs. Do not connect the SLx pins directly to PGND. Instead, use dedicated traces to connect
these pins to the sources of the low-side external MOSFETs. These recommendations offer more accurate VDS
sensing of the external MOSFETs for overcurrent detection.
Minimize the loop length for the high-side and low-side gate drivers. The high-side loop is from the GHx pin of
the device to the high-side power MOSFET gate, then follows the high-side MOSFET source back to the SHx
pin. The low-side loop is from the GLx pin of the device to the low-side power MOSFET gate, then follows the
low-side MOSFET source back to the PGND pin. Gate and source traces should be sufficiently sized to carry the
full IDRIVE current, and layer changes and vias should be avoided. These techniques should reduce inductance in
the gate and source nodes which will help ensure best performance and efficiency. Extra care should be taken
in the low side path as excessive inductance can cause the VGLS regulator to overshoot which could overstress
the FET VGS.
For additional layout guidelines and examples see the Layout Guide for the DRV832x Family of Three-Phase
Smart Gate Drivers application report and the Best Practices for Board Layout of Motor Drivers application
report.
11.1.1 Buck-Regulator Layout Guidelines
Layout is a critical portion of good power supply design. The following guidelines help users design a PCB
with the best power conversion performance, thermal performance, and minimized generation of unwanted
electromagnetic interference (EMI):
• Place the feedback network resistors close to the FB pin and away from the inductor to minimize coupling
   noise into the feedback pin.
• Place the input bypass capacitor close to the VIN pin to decrease copper trace resistance which effects the
   input voltage ripple of the device.
• Place the inductor close to the SW pin to decrease magnetic and electrostatic noise.
• Place the output capacitor close to the junction of the inductor and the diode. The inductor, diode, and
   COUT trace should be as short as possible to decrease conducted and radiated noise and increase overall
   efficiency.
• Make the ground connection for the diode, CVIN, and COUT as small as possible and tie it to the system
   ground plane in only one spot (preferably at the COUT ground point) to minimize conducted noise in the
   system ground plane.




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For more detail on switching power supply layout considerations refer to the AN-1149 Layout Guidelines for
Switching Power Supplies application report.




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11.2 Layout Example

                                                                                                          S                   D



                                                                                                          S                   D



                                                                                                          S                   D



                                                                                                          G                   D




                                                  ENABLE




                                                  nFAULT
                                        DVDD




                                                                 VREF
                                                  nSCS
                                                  SCLK
                             INHC



                             INHA
                             INHB
                             INLC



                             INLA
                             INLB




                                                                                      SOC
                                                                               SOB
                                                                        SOA
                                                  CAL




                                                                                                                                    OUTC
                                                  SDI
                                                  SO
    VO




                                                                                                          D                   G



                                                                                                          D                   S



                                                                                                          D                   S
                                                33 ENABLE




                                                28 nFAULT
                                                27 DGND
                                                35 AGND
                                                36 DVDD




                                                26 VREF
                                                32 nSCS
                                                31 SCLK

                                                29 SDO




                                                25 SOA
                                                34 CAL




                                                30 SDI




                                                                                                          D                   S


                                     INHA 37                                  24     SOB
                                      INLA 38                                 23     SOC
                                     INHB 39                                  22     SNC
                                      INLB 40                                 21     SPC                  D                   G
                                     INHC 41                                  20     GLC
                                      INLC 42                                 19     SHC
                                                   Thermal Pad                                            D                   S
                                    BGND 43                                   18     GHC
                                        CB 44                                 17     GHB
                                        SW 45                                 16     SHB
                                                                                                          D                   S
                                        NC 46                                 15     GLB
                                       VIN 47                                 14     SPB
                                   nSHDN 48                                   13     SNB                  D                   S
                                                   GLA 10
                                                   SPA 11
                                                  SNA 12
                                                  SHA 9
                                                  GHA 8
                                                VDRAIN 7
                                                    VM 6
                                                  VCP 5
                                                  CPH 4
                                                   CPL 3
                                                 PGND 2
                                                    FB 1




                                                                                                                                    OUTB
                                                                                                          S                   D



                                                                                                          S                   D



                                                                                                          S                   D



                                                                                                          G                   D




                                                                                                          S                   D



                                                                                                          S                   D



                                                                                                          S                   D



                                                                                                          G                   D     OUTA




                                                                                                          D                   G



                                                                                                          D                   S



                                                                                                          D                   S



                                                                                                          D                   S




                                                       Figure 11-1. Layout Example



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12 Device and Documentation Support
12.1 Device Support
12.1.1 Device Nomenclature
The following figure shows a legend for interpreting the complete device name:

                                                DRV83   (2)   (3)   (R)   (S)   (RGZ) (R)


                    Prefix                                                                  Tape and Reel
                    DRV83 ± Three Phase Brushless DC                                        R ± Tape and Reel
                                                                                            T ± Small Tape and Reel

                                                                                            Package
                                                                                            RTV ± 5 × 5 × 0.75 mm QFN
                    Series
                                                                                            RTA ± 6 x 6 × 0.75 mm QFN
                    2 ± 60 V device
                                                                                            RHA ± 6 x 6 × 0.9 mm QFN
                    5 ± 100 V device
                                                                                            RGZ ± 7 × 7 × 0.9 mm QFN

                   Sense amplifiers                                                         Interface
                   0 ± No sense amplifiers                                                  S ± SPI interface
                   3 ± 3x sense amplifiers                                                  H ± Hardware interface

                                                                                            Buck Regulator
                                                                                            [blank] ± No buck regulator
                                                                                            R ± Buck regulator

12.2 Documentation Support
12.2.1 Related Documentation
•    Texas Instruments, Architecture for Brushless-DC Gate Drive Systems application report
•    Texas Instruments, LMR16006 SIMPLE SWITCHER® 60 V 0.6 A Buck Regulators With High Efficiency
     Eco-mode data sheet
•    Texas Instruments, Layout Guide for the DRV832x Family of Three-Phase Smart Gate Drivers application
     report
•    Texas Instruments, AN-1149 Layout Guidelines for Switching Power Supplies application report
•    Texas Instruments, Understanding IDRIVE and TDRIVE In TI Motor Gate Drivers application report
•    Texas Instruments, Reduce Motor Drive BOM and PCB Area with TI Smart Gate Drive TI TechNote
•    Texas Instruments, Reducing EMI Radiated Emissions with TI Smart Gate Drive TI TechNote
•    Texas Instruments, Motor Drive Protection With TI Smart Gate Drive TI TechNote
•    Texas Instruments, QFN/SON PCB Attachment application report
•    Texas Instruments, Cut-Off Switch in High-Current Motor-Drive Applications application report
•    Texas Instruments, Hardware Design Considerations for an Efficient Vacuum Cleaner using BLDC Motor
     application report
•    Texas Instruments, Hardware Design Considerations for an Electric Bicycle using BLDC Motor application
     report
•    Texas Instruments, Sensored 3-Phase BLDC Motor Control Using MSP430™ application report
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.



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12.5 Trademarks
Eco-mode™, NexFET™, and MSP430™ are trademarks of Texas Instruments.
TI E2E™ is a trademark of Texas Instruments.
SIMPLE SWITCHER® is a registered trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
                    This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
                    with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
                    ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
                    be more susceptible to damage because very small parametric changes could cause the device not to meet its published
                    specifications.


12.7 Glossary
 TI Glossary             This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.




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PACKAGING INFORMATION

 Orderable part number   Status   Material type   Package | Pins    Package qty | Carrier   RoHS       Lead finish/         MSL rating/        Op temp (°C)   Part marking
                           (1)         (2)                                                   (3)       Ball material        Peak reflow                            (6)
                                                                                                            (4)                  (5)

     DRV8320HRTVR        Active    Production     WQFN (RTV) | 32    3000 | LARGE T&R        Yes         NIPDAU          Level-1-260C-UNLIM     -40 to 125     DRV8320H
    DRV8320HRTVR.A       Active    Production     WQFN (RTV) | 32    3000 | LARGE T&R        Yes         NIPDAU          Level-1-260C-UNLIM     -40 to 125     DRV8320H
     DRV8320HRTVT        Active    Production     WQFN (RTV) | 32     250 | SMALL T&R        Yes         NIPDAU          Level-1-260C-UNLIM     -40 to 125     DRV8320H
    DRV8320HRTVT.A       Active    Production     WQFN (RTV) | 32     250 | SMALL T&R        Yes         NIPDAU          Level-1-260C-UNLIM     -40 to 125     DRV8320H
   DRV8320HRTVTG4        Active    Production     WQFN (RTV) | 32     250 | SMALL T&R        Yes         NIPDAU          Level-1-260C-UNLIM     -40 to 125     DRV8320H
  DRV8320HRTVTG4.A       Active    Production     WQFN (RTV) | 32     250 | SMALL T&R        Yes         NIPDAU          Level-1-260C-UNLIM     -40 to 125     DRV8320H
    DRV8320RHRHAR        Active    Production     VQFN (RHA) | 40    2500 | LARGE T&R        Yes         NIPDAU          Level-1-260C-UNLIM     -40 to 125       DRV
                                                                                                                                                                8320RH
   DRV8320RHRHAR.A       Active    Production     VQFN (RHA) | 40    2500 | LARGE T&R        Yes         NIPDAU          Level-1-260C-UNLIM     -40 to 125       DRV
                                                                                                                                                                8320RH
    DRV8320RHRHAT        Active    Production     VQFN (RHA) | 40     250 | SMALL T&R        Yes         NIPDAU          Level-1-260C-UNLIM     -40 to 125       DRV
                                                                                                                                                                8320RH
   DRV8320RHRHAT.A       Active    Production     VQFN (RHA) | 40     250 | SMALL T&R        Yes         NIPDAU          Level-1-260C-UNLIM     -40 to 125       DRV
                                                                                                                                                                8320RH
    DRV8320RSRHAR        Active    Production     VQFN (RHA) | 40    2500 | LARGE T&R        Yes         NIPDAU          Level-1-260C-UNLIM     -40 to 125       DRV
                                                                                                                                                                8320RS
   DRV8320RSRHAR.A       Active    Production     VQFN (RHA) | 40    2500 | LARGE T&R        Yes         NIPDAU          Level-1-260C-UNLIM     -40 to 125       DRV
                                                                                                                                                                8320RS
    DRV8320RSRHAT        Active    Production     VQFN (RHA) | 40     250 | SMALL T&R        Yes         NIPDAU          Level-1-260C-UNLIM     -40 to 125       DRV
                                                                                                                                                                8320RS
   DRV8320RSRHAT.A       Active    Production     VQFN (RHA) | 40     250 | SMALL T&R        Yes         NIPDAU          Level-1-260C-UNLIM     -40 to 125       DRV
                                                                                                                                                                8320RS
     DRV8320SRTVR        Active    Production     WQFN (RTV) | 32    3000 | LARGE T&R        Yes         NIPDAU          Level-1-260C-UNLIM     -40 to 125     DRV8320S
    DRV8320SRTVR.A       Active    Production     WQFN (RTV) | 32    3000 | LARGE T&R        Yes         NIPDAU          Level-1-260C-UNLIM     -40 to 125     DRV8320S
     DRV8320SRTVT        Active    Production     WQFN (RTV) | 32     250 | SMALL T&R        Yes      Call TI | Nipdau   Level-2-260C-1 YEAR    -40 to 125     DRV8320S
    DRV8320SRTVT.A       Active    Production     WQFN (RTV) | 32     250 | SMALL T&R        Yes         NIPDAU          Level-2-260C-1 YEAR    -40 to 125     DRV8320S
     DRV8323HRTAR        Active    Production     WQFN (RTA) | 40    2500 | LARGE T&R        Yes         NIPDAU          Level-1-260C-UNLIM     -40 to 125     DRV8323H
    DRV8323HRTAR.A       Active    Production     WQFN (RTA) | 40    2500 | LARGE T&R        Yes         NIPDAU          Level-1-260C-UNLIM     -40 to 125     DRV8323H
     DRV8323HRTAT        Active    Production     WQFN (RTA) | 40     250 | SMALL T&R        Yes         NIPDAU          Level-1-260C-UNLIM     -40 to 125     DRV8323H
    DRV8323HRTAT.A       Active    Production     WQFN (RTA) | 40     250 | SMALL T&R        Yes         NIPDAU          Level-1-260C-UNLIM     -40 to 125     DRV8323H
    DRV8323RHRGZR        Active    Production     VQFN (RGZ) | 48    2500 | LARGE T&R        Yes         NIPDAU          Level-2-260C-1 YEAR    -40 to 125    DRV8323RH



                                                                                    Addendum-Page 1
                                                                                                                                                                     PACKAGE OPTION ADDENDUM

       www.ti.com                                                                                                                                                                                                    6-Feb-2026




       Orderable part number          Status     Material type      Package | Pins      Package qty | Carrier       RoHS             Lead finish/               MSL rating/          Op temp (°C)               Part marking
                                        (1)            (2)                                                            (3)            Ball material              Peak reflow                                           (6)
                                                                                                                                          (4)                       (5)

        DRV8323RHRGZR.A               Active      Production       VQFN (RGZ) | 48       2500 | LARGE T&R            Yes               NIPDAU           Level-2-260C-1 YEAR            -40 to 125               DRV8323RH
         DRV8323RHRGZT                Active      Production       VQFN (RGZ) | 48        250 | SMALL T&R            Yes               NIPDAU           Level-2-260C-1 YEAR            -40 to 125               DRV8323RH
        DRV8323RHRGZT.A               Active      Production       VQFN (RGZ) | 48        250 | SMALL T&R            Yes               NIPDAU           Level-2-260C-1 YEAR            -40 to 125               DRV8323RH
         DRV8323RSRGZR                Active      Production       VQFN (RGZ) | 48       2500 | LARGE T&R            Yes               NIPDAU           Level-2-260C-1 YEAR            -40 to 125               DRV8323RS
        DRV8323RSRGZR.A               Active      Production       VQFN (RGZ) | 48       2500 | LARGE T&R            Yes               NIPDAU           Level-2-260C-1 YEAR            -40 to 125               DRV8323RS
        DRV8323RSRGZRG4               Active      Production       VQFN (RGZ) | 48       2500 | LARGE T&R            Yes               NIPDAU           Level-2-260C-1 YEAR            -40 to 125               DRV8323RS
       DRV8323RSRGZRG4.A              Active      Production       VQFN (RGZ) | 48       2500 | LARGE T&R            Yes               NIPDAU           Level-2-260C-1 YEAR            -40 to 125               DRV8323RS
         DRV8323RSRGZT                Active      Production       VQFN (RGZ) | 48        250 | SMALL T&R            Yes               NIPDAU           Level-2-260C-1 YEAR            -40 to 125               DRV8323RS
        DRV8323RSRGZT.A               Active      Production       VQFN (RGZ) | 48        250 | SMALL T&R            Yes               NIPDAU           Level-2-260C-1 YEAR            -40 to 125               DRV8323RS
          DRV8323SRTAR                Active      Production       WQFN (RTA) | 40       2500 | LARGE T&R            Yes               NIPDAU            Level-1-260C-UNLIM            -40 to 125                DRV8323S
         DRV8323SRTAR.A               Active      Production       WQFN (RTA) | 40       2500 | LARGE T&R            Yes               NIPDAU            Level-1-260C-UNLIM            -40 to 125                DRV8323S
         DRV8323SRTARG4               Active      Production       WQFN (RTA) | 40       2500 | LARGE T&R            Yes               NIPDAU            Level-1-260C-UNLIM            -40 to 125                DRV8323S
        DRV8323SRTARG4.A              Active      Production       WQFN (RTA) | 40       2500 | LARGE T&R            Yes               NIPDAU            Level-1-260C-UNLIM            -40 to 125                DRV8323S
          DRV8323SRTAT                Active      Production       WQFN (RTA) | 40        250 | SMALL T&R            Yes               NIPDAU            Level-1-260C-UNLIM            -40 to 125                DRV8323S
         DRV8323SRTAT.A               Active      Production       WQFN (RTA) | 40        250 | SMALL T&R            Yes               NIPDAU            Level-1-260C-UNLIM            -40 to 125                DRV8323S

(1)
      Status: For more details on status, see our product life cycle.

(2)
   Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

(3)
      RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

(4)
   Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.

(5)
  MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

(6)
      Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.




                                                                                                          Addendum-Page 2
                                                                                                                                                                      PACKAGE OPTION ADDENDUM

    www.ti.com                                                                                                                                                                                                     6-Feb-2026




Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.




                                                                                                          Addendum-Page 3
                                                                               PACKAGE MATERIALS INFORMATION

www.ti.com                                                                                                                                       18-Jun-2025



TAPE AND REEL INFORMATION

       REEL DIMENSIONS                                                                      TAPE DIMENSIONS
                                                                                       K0       P1



                                                                                                                      B0 W
                                        Reel
                                      Diameter
                                                                                    Cavity           A0
                                                                A0   Dimension designed to accommodate the component width
                                                                B0   Dimension designed to accommodate the component length
                                                                K0   Dimension designed to accommodate the component thickness
                                                                W    Overall width of the carrier tape
                                                                P1   Pitch between successive cavity centers


                                       Reel Width (W1)
                              QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

                                                                                                     Sprocket Holes


                                                 Q1        Q2          Q1    Q2

                                                 Q3        Q4          Q3    Q4                  User Direction of Feed



                                                            Pocket Quadrants


*All dimensions are nominal
             Device           Package Package Pins              SPQ        Reel   Reel   A0                 B0         K0     P1     W     Pin1
                               Type Drawing                              Diameter Width (mm)               (mm)       (mm)   (mm)   (mm) Quadrant
                                                                           (mm) W1 (mm)
     DRV8320HRTVR             WQFN      RTV           32        3000        330.0        12.4        5.3    5.3       1.1    8.0    12.0    Q2
     DRV8320HRTVT             WQFN      RTV           32         250        180.0        12.4        5.3    5.3       1.1    8.0    12.0    Q2
   DRV8320HRTVTG4             WQFN      RTV           32         250        180.0        12.4        5.3    5.3       1.1    8.0    12.0    Q2
    DRV8320RHRHAR              VQFN     RHA           40        2500        330.0        16.4        6.3    6.3       1.1    12.0   16.0    Q2
    DRV8320RHRHAT              VQFN     RHA           40         250        180.0        16.4        6.3    6.3       1.1    12.0   16.0    Q2
    DRV8320RSRHAR              VQFN     RHA           40        2500        330.0        16.4        6.3    6.3       1.1    12.0   16.0    Q2
    DRV8320RSRHAT              VQFN     RHA           40         250        180.0        16.4        6.3    6.3       1.1    12.0   16.0    Q2
     DRV8320SRTVR             WQFN      RTV           32        3000        330.0        12.4        5.3    5.3       1.1    8.0    12.0    Q2
     DRV8320SRTVT             WQFN      RTV           32         250        180.0        12.4        5.3    5.3       1.1    8.0    12.0    Q2
     DRV8323HRTAR             WQFN      RTA           40        2500        330.0        16.4        6.3    6.3       1.1    12.0   16.0    Q2
     DRV8323HRTAT             WQFN      RTA           40         250        180.0        16.4        6.3    6.3       1.1    12.0   16.0    Q2
    DRV8323RHRGZR              VQFN     RGZ           48        2500        330.0        16.4        7.3    7.3       1.1    12.0   16.0    Q2
    DRV8323RHRGZT              VQFN     RGZ           48         250        180.0        16.4        7.3    7.3       1.1    12.0   16.0    Q2
    DRV8323RSRGZR              VQFN     RGZ           48        2500        330.0        16.4        7.3    7.3       1.1    12.0   16.0    Q2
  DRV8323RSRGZRG4              VQFN     RGZ           48        2500        330.0        16.4        7.3    7.3       1.1    12.0   16.0    Q2
    DRV8323RSRGZT              VQFN     RGZ           48         250        180.0        16.4        7.3    7.3       1.1    12.0   16.0    Q2




                                                                       Pack Materials-Page 1
                                                           PACKAGE MATERIALS INFORMATION

www.ti.com                                                                                                         18-Jun-2025



             Device   Package Package Pins   SPQ       Reel   Reel   A0           B0     K0     P1     W     Pin1
                       Type Drawing                  Diameter Width (mm)         (mm)   (mm)   (mm)   (mm) Quadrant
                                                       (mm) W1 (mm)
    DRV8323SRTAR      WQFN     RTA     40    2500      330.0     16.4      6.3   6.3    1.1    12.0   16.0    Q2
   DRV8323SRTARG4     WQFN     RTA     40    2500      330.0     16.4      6.3   6.3    1.1    12.0   16.0    Q2
     DRV8323SRTAT     WQFN     RTA     40    250       180.0     16.4      6.3   6.3    1.1    12.0   16.0    Q2




                                                   Pack Materials-Page 2
                                                                PACKAGE MATERIALS INFORMATION

www.ti.com                                                                                                              18-Jun-2025



 TAPE AND REEL BOX DIMENSIONS




                                                               Width (mm)
                                                                              H
                      W




                                                          L




*All dimensions are nominal
             Device           Package Type   Package Drawing   Pins         SPQ    Length (mm)   Width (mm)   Height (mm)
     DRV8320HRTVR                WQFN             RTV           32          3000      346.0        346.0         33.0
     DRV8320HRTVT                WQFN             RTV           32          250       182.0        182.0         20.0
    DRV8320HRTVTG4               WQFN             RTV           32          250       182.0        182.0         20.0
    DRV8320RHRHAR                VQFN             RHA           40          2500      367.0        367.0         38.0
    DRV8320RHRHAT                VQFN             RHA           40          250       182.0        182.0         20.0
    DRV8320RSRHAR                VQFN             RHA           40          2500      367.0        367.0         38.0
    DRV8320RSRHAT                VQFN             RHA           40          250       182.0        182.0         20.0
     DRV8320SRTVR                WQFN             RTV           32          3000      346.0        346.0         33.0
     DRV8320SRTVT                WQFN             RTV           32          250       210.0        185.0         35.0
     DRV8323HRTAR                WQFN             RTA           40          2500      367.0        367.0         38.0
     DRV8323HRTAT                WQFN             RTA           40          250       182.0        182.0         20.0
    DRV8323RHRGZR                VQFN             RGZ           48          2500      367.0        367.0         38.0
    DRV8323RHRGZT                VQFN             RGZ           48          250       210.0        185.0         35.0
    DRV8323RSRGZR                VQFN             RGZ           48          2500      367.0        367.0         38.0
   DRV8323RSRGZRG4               VQFN             RGZ           48          2500      367.0        367.0         38.0
    DRV8323RSRGZT                VQFN             RGZ           48          250       210.0        185.0         35.0
     DRV8323SRTAR                WQFN             RTA           40          2500      367.0        367.0         38.0
    DRV8323SRTARG4               WQFN             RTA           40          2500      367.0        367.0         38.0




                                                        Pack Materials-Page 3
                                                        PACKAGE MATERIALS INFORMATION

www.ti.com                                                                                                   18-Jun-2025



             Device   Package Type   Package Drawing   Pins     SPQ     Length (mm)   Width (mm)   Height (mm)
     DRV8323SRTAT        WQFN             RTA           40      250        182.0        182.0         20.0




                                                Pack Materials-Page 4
                                                                  GENERIC PACKAGE VIEW
RHA 40                                                                     VQFN - 1 mm max height
6 x 6, 0.5 mm pitch                                                         PLASTIC QUAD FLATPACK - NO LEAD




               This image is a representation of the package family, actual package may vary.
                             Refer to the product data sheet for package details.




                                                                                                   4225870/A




                                                    www.ti.com
                                                                                                              PACKAGE OUTLINE
RTV0032E                                                         SCALE 3.000
                                                                                                        WQFN - 0.8 mm max height
                                                                                                              PLASTIC QUAD FLATPACK - NO LEAD


                                                      5.15                                        B
                           A
                                                      4.85




         PIN 1 INDEX AREA

                                                                                                 5.15
                                                                                                 4.85




                                                                                                                           SIDE WALL LEAD
                                                                                                                          METAL THICKNESS
                 0.8                                                                                                            DIM A
                 0.7                                                                                                     OPTION 1    OPTION 2
                                                                                                        C                  0.1         0.2

                                                                                                              SEATING PLANE
                    0.05
                    0.00                                                                                     0.08 C
                                                     2X 3.5                                                                             (DIM A) TYP
                                                     3.45 0.1                                                         (0.2) TYP
                                      9                                                16        EXPOSED
                                                                                                 THERMAL PAD
               28X 0.5
                               8
                                                                                            17




                   2X                                                                            SYMM
                                                         33
                   3.5




                                                                                                            0.30
                                                                                                      32X
                                                                                                            0.18
                                                                                            24              0.1    C A B
                               1
                                                                                                            0.05    C
                   PIN 1 ID
                (OPTIONAL)             32                                             25
                                                     SYMM
                                                                                0.5
                                                                32X
                                                                                0.3
                                                                                                                                  4225196/A 08/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
   per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.




                                                                               www.ti.com
                                                                                        EXAMPLE BOARD LAYOUT
RTV0032E                                                                                         WQFN - 0.8 mm max height
                                                                                                      PLASTIC QUAD FLATPACK - NO LEAD



                                                                  ( 3.45)

                                                                    SYMM
                                         32                                                      25
                32X (0.6)




                             1                                                                                  24

            32X (0.24)



                                                                                                                  (1.475)
                28X (0.5)

                                                                         33                                                 SYMM


                                                                                                                                   (4.8)
             ( 0.2) TYP
                     VIA




                             8                                                                                  17
                (R0.05)
                   TYP


                                              9                                                 16
                                                                              (1.475)

                                                                    (4.8)

                                                     LAND PATTERN EXAMPLE
                                                                 SCALE:18X

                              0.07 MAX                                                  0.07 MIN
                          ALL AROUND                                                ALL AROUND

                                                                                                                SOLDER MASK
                                                     METAL                                                      OPENING


                                                      SOLDER MASK                                                    METAL UNDER
                                                      OPENING                                                        SOLDER MASK

                                 NON SOLDER MASK
                                                                                              SOLDER MASK
                                     DEFINED
                                                                                                DEFINED
                                   (PREFERRED)

                                                          SOLDER MASK DETAILS
                                                                                                                            4225196/A 08/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
   number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
   on this view. It is recommended that vias under paste be filled, plugged or tented.




                                                                       www.ti.com
                                                                                EXAMPLE STENCIL DESIGN
RTV0032E                                                                                   WQFN - 0.8 mm max height
                                                                                                PLASTIC QUAD FLATPACK - NO LEAD




                                              4X ( 1.49)
                (R0.05) TYP                                           (0.845)
                                    32                                                     25
          32X (0.6)




                       1                                                                                  24

       32X (0.24)




           28X (0.5)
                                                                                                            (0.845)
                                                                                                                      SYMM
                                                                      33

                                                                                                                             (4.8)




                       8                                                                                  17


             METAL
             TYP



                                         9                                            16
                                                             SYMM


                                                              (4.8)


                                                 SOLDER PASTE EXAMPLE
                                               BASED ON 0.125 mm THICK STENCIL

                                                   EXPOSED PAD 33:
                                 75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
                                                      SCALE:20X




                                                                                                                  4225196/A 08/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
  design recommendations.




                                                                 www.ti.com
                                                                  GENERIC PACKAGE VIEW
RGZ 48                                                                     VQFN - 1 mm max height
7 x 7, 0.5 mm pitch                                                         PLASTIC QUADFLAT PACK- NO LEAD




      Images above are just a representation of the package family, actual package may vary.
      Refer to the product data sheet for package details.

                                                                                                  4224671/A




                                                    www.ti.com
                                                                                                  PACKAGE OUTLINE
RGZ0048A                                                                                         VQFN - 1 mm max height
                                                                                           PLASTIC QUADFLAT PACK- NO LEAD

                                                         7.1                           A
                                B                        6.9




                                                                                                                   (0.1) TYP

                                                                                       7.1            SIDE WALL DETAIL
            PIN 1 INDEX AREA                                                           6.9       OPTIONAL METAL THICKNESS



                                                                                                                          (0.45) TYP


                                                                                                       CHAMFERED LEAD
                                                                                                      CORNER LEAD OPTION

                      1 MAX
                                                                                        C

                                                                                             SEATING PLANE
                           0.05                                                              0.08 C
                           0.00
                                                      2X 5.5

                                                       5.15±0.1                                                    (0.2) TYP
                                         13                                  24
                      44X 0.5
                                    12
                                                                                  25
                                                                                        SEE SIDE WALL
                                                                                               DETAIL




                         2X                                                       SYMM
                         5.5




                                    1                                             36
                      PIN1 ID                                                              48X 0.30
                                                                                               0.18
                                          48                                37
                  (OPTIONAL)
                                                       SYMM                                    0.1    C A B
                                                                  48X 0.5
                                                                      0.3                      0.05    C
          SEE LEAD OPTION

                                                                                                                  4219044/D 02/2022

NOTES:

 1.   All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
      per ASME Y14.5M.
 2.   This drawing is subject to change without notice.
 3.   The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.




                                                               www.ti.com
                                                                                     EXAMPLE BOARD LAYOUT
RGZ0048A                                                                                        VQFN - 1 mm max height
                                                                                          PLASTIC QUADFLAT PACK- NO LEAD

                                                                     2X (6.8)
                                                                     ( 5.15)
                                                                     SYMM
                    48X (0.6)            48                                                         37

           48X (0.24)

      44X (0.5)                 1
                                                                                                                  36




             2X       SYMM                                                                                                    2X
            (5.5)                                                                                                            (6.8)

                                                                                                                     2X
                                                                                                                   (1.26)




                                                                                                                     2X
                                                                                                                   (1.065)

 (R0.05)
   TYP
                                                                                                                  25
                            12
             21X (Ø0.2) VIA
                  TYP

                                        13                                                            24
                                                           2X (1.26)                                       2X (1.065)
                                                                     2X (5.5)
                                                        LAND PATTERN EXAMPLE
                                                                     SCALE: 15X

                                          0.07 MAX                    0.07 MIN                    SOLDER MASK
                                        ALL AROUND                  ALL AROUND                    OPENING

                                 EXPOSED METAL                                                EXPOSED METAL
                                                                    METAL
                                    SOLDER MASK                                                METAL UNDER
                                        OPENING   NON SOLDER MASK                              SOLDER MASK
                                                                                SOLDER MASK
                                                      DEFINED                     DEFINED
                                                    (PREFERRED)
                                                       SOLDER MASK DETAILS                                              4219044/D 02/2022

NOTES: (continued)

 4.   This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
      number SLUA271 (www.ti.com/lit/slua271).
 5.   Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
      on this view. It is recommended that vias under paste be filled, plugged or tented.




                                                                www.ti.com
                                                                                EXAMPLE STENCIL DESIGN
RGZ0048A                                                                                      VQFN - 1 mm max height
                                                                                        PLASTIC QUADFLAT PACK- NO LEAD




                                                               2X (6.8)
                                                                SYMM                             ( 1.06)
                   48X (0.6)        48                                                            37

          48X (0.24)

      44X (0.5)                1
                                                                                                              36




            2X       SYMM                                                                                               2X
           (5.5)                                                                                                 2X (6.8)
                                                                                                               (0.63)


                                                                                                                 2X
                                                                                                               (1.26)




(R0.05)
  TYP
                                                                                                              25
                           12




                                   13                                            2X                24
                                                        2X (0.63)
                                                                               (1.26)
                                                                2X (5.5)

                                                    SOLDER PASTE EXAMPLE
                                                  BASED ON 0.125 mm THICK STENCIL

                                                            EXPOSED PAD
                                                   67% PRINTED COVERAGE BY AREA
                                                             SCALE: 15X



                                                                                                                   4219044/D 02/2022

NOTES: (continued)

 6.    Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
       design recommendations.




                                                              www.ti.com
                                         IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
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