{
  "schema_version": 1,
  "type": "skill",
  "slug": "electrical-engineering",
  "title": "electrical engineering",
  "brief": "Conventions, defaults, and domain knowledge that electrical engineers care about — especially in PCB / hardware-design contexts. Read before designing any UI, CLI, or file format that touches PCB dime",
  "version": "1.0.0",
  "tags": [],
  "license": "MIT",
  "sample_prompts": [
    {
      "label": "EE defaults",
      "prompt": "What unit defaults should I use in this PCB tool?"
    },
    {
      "label": "Refdes lookup",
      "prompt": "What's the refdes convention for an inductor?"
    },
    {
      "label": "JLCPCB DRC",
      "prompt": "What are the JLCPCB DRC defaults for a 4-layer board?"
    },
    {
      "label": "BOM ordering",
      "prompt": "What's the canonical column ordering for a BOM CSV?"
    },
    {
      "label": "Package family",
      "prompt": "Is QFN-16 in the same family as DFN-16?"
    },
    {
      "label": "Mils vs mm",
      "prompt": "Should this trace-width input default to mils or mm?"
    }
  ],
  "source_path": "SKILL.md",
  "readme": "---\nname: electrical-engineering\ndescription: >\n  Conventions, defaults, and domain knowledge that electrical\n  engineers care about — especially in a PCB / hardware-design\n  context. Read before designing any UI, CLI, or file format that\n  touches PCB dimensions, trace specs, datasheets, fabrication\n  files, or EE terminology. The Adom ecosystem is\n  EE-centric — defaults, unit choices, labels, and vocabulary\n  should feel native to someone who lives in datasheets.\n  Trigger words: electrical engineering, EE, PCB, trace width,\n  clearance, mils, mm, imperial, metric, tscircuit, kicad, fusion\n  electronics, datasheet, component, copper weight, ohms, stackup,\n  DRC, BOM, gerber, CPL, pick and place, JLCPCB, Mouser, DigiKey,\n  silkscreen, pad, via, drill, stencil, reflow.\n---\n\n# Electrical Engineering Conventions\n\nDefaults, naming, and domain knowledge for tools / UIs that will be\nused by EEs. Getting these right makes Adom tools feel NATIVE to an\nengineer who lives in datasheets. Getting them wrong flags the tool\nas \"clearly not built by someone who does this for a living.\"\n\n---\n\n## 1. Units\n\n### 1a. Primary metric (mm), secondary always available in mils + inches\n\nPCB work in North America is a hybrid world:\n\n- **Mechanical / board outline / component dimensions**: metric (mm)\n  is the standard. tscircuit, KiCad, and Fusion Electronics all\n  default to mm.\n- **Trace widths, pad dimensions, clearances, drill sizes**: still\n  commonly spec'd in **mils** (thousandths of an inch). A 10 mil\n  trace, a 6 mil / 6 mil trace/space spec, a 0.8 mm pitch BGA with\n  31.5 mil pad diameter. Datasheets mix the two all day long.\n- **Inches**: used occasionally for board-level mechanical refs\n  (e.g. \"fits in a 2-inch enclosure\").\n\n**In any measurement UI / report / CLI output: primary in mm,\nSECONDARY UNITS DEFAULT TO MILS, not \"None\".** Showing the mil\nconversion in brackets after every mm value (\"2.54 mm (100 mil)\") is\nnon-negotiable polish — American EEs mentally translate the mil\nnumber faster than the mm one, and hiding it adds friction.\n\nConversion: **1 mil = 0.0254 mm** (exactly). Multiply mm by 39.37 to\nget mils, divide mils by 39.37 to get mm.\n\nOther useful conversions:\n- 1 inch = 25.4 mm = 1000 mils\n- 0.1\" pitch (common through-hole) = 2.54 mm = 100 mil\n- 0.05\" pitch = 1.27 mm = 50 mil\n- 0.8 mm pitch BGA = 31.5 mil\n- 0.5 mm pitch QFP = 19.7 mil\n\n### 1b. Precision\n\nPCB feature precision scales with the feature type:\n\n| Feature | Typical precision |\n|---|---|\n| Board dimensions | 0.1 mm (~4 mil) |\n| Component placement | 0.01 mm (~0.4 mil) |\n| Trace width | 0.01 mm or 0.5 mil |\n| Pad dimensions | 0.01 mm |\n| Drill sizes | 0.05 mm or 1 mil |\n\nShow 3 decimal places of mm by default in measurement UIs (equivalent\nto 1 mil). User can dial up or down via a precision selector.\n\n---\n\n## 2. Silkscreen conventions\n\n- Silkscreen must be **white** (top) and **black or off-white** on\n  a black solder-mask (bottom). Other colours look wrong and cause\n  contrast-against-mask problems with fab.\n- Minimum text height: **0.8 mm** (32 mil) for most fab houses, 1.0\n  mm (40 mil) to be safe. Smaller than that and JLCPCB will reject\n  the design.\n- Line width: **0.15 mm** (6 mil) minimum; 0.2 mm (8 mil) safer.\n- **Reference designators** (`U1`, `C3`, `R_REF`): ALWAYS include\n  them on the silkscreen next to every component. Engineers debug\n  by these references; a board without them is ungoogleable at the\n  bench.\n- **Test points** get silk labels: the signal name, not the TP\n  number (`SCK`, `MISO`, not `TP3`).\n\n---\n\n## 3. Reference designator conventions\n\n| Prefix | Kind |\n|---|---|\n| `U` | IC / chip (semiconductor with >2 pins) |\n| `Q` | Transistor (single transistor, BJT or MOSFET) |\n| `D` | Diode (incl. LED, Zener, Schottky) |\n| `R` | Resistor |\n| `C` | Capacitor |\n| `L` | Inductor |\n| `Y`, `X` | Crystal / oscillator |\n| `J`, `P` | Connector (`J` for receptacle/jack, `P` for plug) |\n| `SW`, `S` | Switch |\n| `BT` | Battery |\n| `F` | Fuse |\n| `FB` | Ferrite bead |\n| `MP` | Mounting post / mechanical part |\n| `TP` | Test point |\n| `MC` | Machine contact (Adom Molecule convention) |\n| `JP` | Jumper / solder bridge |\n| `AE` | Antenna |\n\nFollow this in any auto-naming, validation, or search the tool does.\nWhen a tscircuit GLB mesh is named `Box0` but we need to report it\nhuman-readably, walk the ref-designator map from circuit.json\n(`source_component.name`) and use THAT, not the mesh name.\n\n---\n\n## 4. Common chip packages / sizes\n\nWhen a UI needs to describe a chip package visually or validate\nfootprint choice:\n\n| Package | Pin pitch | Typical pin count | Body |\n|---|---|---|---|\n| 0201 | — | 2 | 0.6 × 0.3 mm |\n| 0402 | — | 2 | 1.0 × 0.5 mm |\n| 0603 | — | 2 | 1.6 × 0.8 mm |\n| 0805 | — | 2 | 2.0 × 1.25 mm |\n| 1206 | — | 2 | 3.2 × 1.6 mm |\n| SOT-23 | 0.95 mm | 3 | 2.9 × 1.3 mm |\n| SOT-23-5 | 0.95 mm | 5 | 2.9 × 1.6 mm |\n| SOIC-8 | 1.27 mm | 8 | 5.0 × 4.0 mm |\n| SOIC-14 | 1.27 mm | 14 | 8.7 × 4.0 mm |\n| SSOP-20 | 0.65 mm | 20 | 7.2 × 5.3 mm |\n| TSSOP-20 | 0.65 mm | 20 | 6.5 × 4.4 mm |\n| QFN-32 | 0.5 mm | 32 | 5 × 5 mm |\n| QFN-48 | 0.4 mm | 48 | 7 × 7 mm |\n| QFP-100 | 0.5 mm | 100 | 14 × 14 mm |\n| LQFP-64 | 0.5 mm | 64 | 10 × 10 mm |\n\nUseful when a tool needs to say \"looks like an LQFP-64\" based on\nbounding-box dimensions.\n\n---\n\n## 5. Process / DFM defaults\n\nDefault fabrication minimums for hobbyist-accessible fab houses\n(JLCPCB, PCBWay standard process):\n\n| Spec | Min value | Units |\n|---|---|---|\n| Trace width | 0.127 | mm (5 mil) |\n| Trace spacing | 0.127 | mm (5 mil) |\n| Drill diameter | 0.3 | mm (12 mil) |\n| Via annular ring | 0.15 | mm (6 mil) per side |\n| Pad-to-edge clearance | 0.5 | mm (20 mil) |\n| Silk-to-pad clearance | 0.15 | mm (6 mil) |\n| Mask opening expansion | 0.05 | mm per side |\n\nUse these as DRC defaults; let the user tighten them for a premium\nprocess if desired.\n\n---\n\n## 6. BOM / supplier part numbers\n\n- **LCSC** (JLCPCB's storefront) part numbers look like `C12345` —\n  always the most complete supply for JLCPCB assembly.\n- **Digi-Key** part numbers look like `296-1234-5-ND` or\n  `STM32F103RBT6-ND`.\n- **Mouser** part numbers look like `511-STM32F103RBT6`.\n- **Manufacturer part number** (MPN) is the canonical identifier —\n  e.g. `STM32F103RBT6`. Always carry MPN in BOM regardless of\n  which supplier you link to.\n\nA tscircuit component may carry multiple:\n```\nsupplierPartNumbers={{\n  jlcpcb: [\"C1519043\"],\n  digikey: [\"iCE40HX1K-VQ100CR-ND\"],\n  mouser: [\"576-ICE40HX1K-VQ100CR\"],\n}}\n```\n\nNote the **array syntax** — tscircuit requires lists, not bare\nstrings.\n\n---\n\n## 7. Net / signal naming conventions\n\n- **Power rails**: `VCC`, `VDD`, `VBUS` (USB), `+5V`, `+3V3`,\n  `+1V2`. Always prefix voltage with `+` and write the decimal as\n  `V` (e.g. `3V3` not `3.3`).\n- **Ground**: `GND`, `AGND` (analog), `DGND` (digital), `PGND`\n  (power return).\n- **Differential pairs**: suffix `_P` / `_N` (positive / negative)\n  or `+` / `−` (USB-style `USB_DP` / `USB_DM`).\n- **Clock signals**: `CLK`, `SCLK`, `SCK`, `MCLK`, `XTAL1` / `XTAL2`\n  for crystal pads.\n- **SPI**: `SCK`, `MOSI`, `MISO`, `CS` / `SS`.\n- **I²C**: `SDA`, `SCL`.\n- **UART**: `TXD`, `RXD`, or `TX`/`RX`.\n- **Reset**: `RESET`, `nRESET` / `RESET_N` (active-low).\n\n---\n\n## 8. 3D board viewer conventions (pads, board, chip)\n\nAny viewer that renders PCB pads together with a 3D chip (alignment\ncheckers, InstaPCB previews, molecule review tools) must follow the\nmechanical convention every EE expects. Get this wrong and the scene\nlooks \"weird\" even when the numbers are right.\n\n### 8a. Z=0 is the top copper layer of the board\n\n- **Pad TOP surface = z=0.** The top of the copper pad sits exactly at\n  z=0. Pads extend DOWNWARD into the board (negative z), not upward.\n  Real copper is ~35 µm (0.035 mm) thick; rendering 0.05 mm is a fine\n  compromise between realism and visibility.\n- **Chip sits ON the pads.** For an SMD component, the chip's seat\n  plane (lowest point of the body / leads that touches the board)\n  lands at z=0.\n- **Thru-hole leads pass THROUGH the board.** Leads exit the bottom of\n  a standard 1.6 mm FR4 board at z ≈ −1.6 mm.\n\n### 8a.i. Read the offset — it tells you the GLB's origin convention\n\nBefore flagging a non-zero seat-Δz as \"broken\", check whether it\nmatches one standard board thickness. **1.6 mm is the default FR4\nthickness** (also 0.8 / 1.0 / 1.2 / 2.0 mm for specialty runs). Common\ninterpretations of the number chipMinZ:\n\n| chipMinZ | Mount type | Meaning |\n|---|---|---|\n| ≈ 0 | SMD | GLB origin at TOP of board. Chip seated on pads ✓ |\n| ≈ +1.6 mm | SMD | GLB origin at BOTTOM of board. Workable — assembly offsets chip by −1.6 mm |\n| ≈ −1.6 mm | thru-hole | Leads clear a standard 1.6 mm board ✓ |\n| ≈ 0 | thru-hole | GLB uses origin-at-bottom convention too — chip seat at top-of-slab, leads at bottom |\n| anything else | either | Probably legit floating / sinking — flag it |\n\nDifferent CAD tools bake different conventions: KiCad and tscircuit\nusually export with z=0 at the top copper; Fusion 360 / SolidWorks\nexports often put z=0 at the bottom of the board model, so the chip\nends up at +board_thickness above ground. Neither is wrong — they\njust need an offset at assembly time.\n\n### 8a.ii. Auto-align for display on convention mismatch\n\nA diagnostic viewer should:\n\n1. **Measure the raw chipMinZ** before any display tweak.\n2. **Auto-shift the chip's wrapper transform** so the chip visually\n   seats on the pads for SMD parts (not thru-hole). Showing a chip\n   floating 1.6 mm in air when we *know* this is a convention offset\n   is misleading — it draws the engineer's eye to the wrong thing.\n3. **Report both** the raw offset (\"was +1.595\") AND the shift\n   applied, with an explanation of WHY, in the HUD.\n4. **Expose a provenance panel** listing every pipeline step — source\n   file names, parsed pad count, hidden glTF nodes, wrapper scaling,\n   raw bbox, applied shift — so the engineer can audit how the\n   numbers were arrived at.\n5. **Never auto-shift for thru-hole** — those leads genuinely dip\n   below z=0 and the viewer shouldn't hide that.\n\nThis replaces the earlier \"never auto-correct\" rule with a narrower\none: **never auto-correct silently.** Auto-aligning for display is\nfine when we can attribute the shift to a known convention and show\nthe attribution next to the aligned view.\n\n### 8b. Only one set of pads on screen\n\nWhen loading a GLB that bakes in its own demo PCB (InstaPCB-style\ntest fixtures that carry `board_pad` / `board_PCB` / `board_fr4` /\n`board_soldermask` / `board_silkscreen` meshes inside the chip GLB),\n**hide those baked-in meshes before rendering** so the only pads on\nscreen are the ones from the real KiCad footprint. Two competing pad\nsets in the same scene are the #1 source of \"this viewer looks\nwrong\" feedback — and the baked-in pads almost never match the real\nfootprint anyway.\n\nMatch by the mesh's OWN name AND by ancestor names. glTF exporters\noften wrap meaningful mesh names (`board_pad`, `board_PCB`) under\ncryptic node names (`=>[0:1:1:3]`), so ancestor-only filters miss\nthem.\n\n### 8c. No auto-correction in a diagnostic viewer\n\nIf a chip is floating 0.4 mm above its pads, do NOT silently translate\nit down to touch. The engineer is signing off on the STEP model\nbeing correct; hiding the offset defeats the purpose of the check.\nSurface the Δz in a HUD with colour-coded acceptance bands (green /\nyellow / red) and let the engineer decide. This rule applies to\nevery diagnostic view — see `app-creator` §7e.\n\n### 8d. Always annotate pin 1 — and bake it into the GLB once it's verified\n\nPin 1 is the canonical reference corner for every chip. Datasheets\nmark it with a dot, chamfer, notch, or silk triangle. Any 3D viewer\nthat shows a chip on pads MUST give pin 1 a bright, unmistakable\noverlay (red ring, beam, or arrow) so alignment against the chip's\npin-1 marker is a one-look check. Relying on \"you can see the\nmarker in the GLB texture\" is not good enough at zoom / angle.\n\n**Persist the registration into the chip GLB itself.** After the\nengineer has visually verified pin-1 alignment via an overlay,\nbake a small red hemispherical dot (~1 mm diameter, IC-convention)\nonto the chip's top surface at the corner nearest pin 1 — NOT\ndirectly above the pin-1 pad, that's not the manufacturer\nconvention. Save the result as `<stem>-pin1.glb` next to the source.\nEvery downstream tool (board preview, molecule review, InstaPCB)\nthen renders the mark automatically. The chip becomes\nself-identifying on every future project; no engineer has to guess\n\"which corner is pin 1?\" during layout, rework, or bench debug.\n\nPairing rules:\n- The footprint `.kicad_mod` must have a silk-screen pin-1 marker on\n  `F.SilkS` near pin 1 (circle or triangle ~0.5 mm). KiCad's library\n  ships this on nearly every footprint; verify on custom ones.\n- Board silk flows the footprint's silk into gerbers automatically —\n  nothing new to do here once (1) and (2) are in place.\n\n### 8e. Never align a chip to a wrong-family footprint\n\nA QFN-24 GLB on an LQFP-48 footprint cannot physically be assembled\nand any resulting \"alignment\" view is a lie. 3D alignment viewers\nmust parse both filenames for package family + pin count and\n**refuse** to render a mismatched pair. Family aliases:\n\n| Same family |\n|---|\n| LQFP / TQFP / QFP |\n| QFN / DFN |\n| TSSOP / SSOP / SOIC / SOP / SO |\n| DIP / PDIP |\n| SOT / SOD |\n| BGA / CSP |\n\nThe refusal should surface in both the CLI (fail before binding the\nport) and the browser (blocking error banner). Rendering one\nanyway is worse than failing because a screenshot of it will travel\nand mislead someone downstream.\n\n### 8e. Z-up world, right-handed\n\nAdom's 3D convention (shared with KiCad, Fusion Electronics, and the\nInstaPCB pipeline) is **Z-up, right-handed**: +X right, +Y back,\n+Z up. Pads are in the XY plane; chip bodies rise in +Z. GLBs\nloaded from tscircuit / KiCad / Fusion follow the \"1 GLB unit = 1\nmeter\" convention, so scale by 1000 to land in mm-space alongside\nthe footprint.\n\n---\n\n## 9. Checklist — every new EE-touching tool\n\n- [ ] Units: primary mm, secondary MILS by default (not None)?\n- [ ] Mil conversion shown in brackets wherever mm is displayed?\n- [ ] Ref-designator naming convention respected in labels and\n      auto-generated names?\n- [ ] Silkscreen min-size / min-line rules enforced at DRC?\n- [ ] DFM defaults match JLCPCB standard process?\n- [ ] BOM exports include MPN as first-class column, not just\n      supplier-specific?\n- [ ] Net naming follows the standard prefixes (`VCC`, `GND`,\n      differential `_P`/`_N`)?\n- [ ] Reference designators use the canonical prefixes (U/Q/D/R/C/L/…)?\n- [ ] 3D viewer: pad TOP at z=0, chip sits on pads, no auto-correct?\n- [ ] 3D viewer: baked-in demo PCB meshes from GLB hidden before render?\n- [ ] 3D viewer: pin 1 called out with a bright overlay, not just texture?\n- [ ] 3D viewer: package-family + pin-count mismatch blocked (CLI + UI)?\n- [ ] 3D viewer: pin-1 registration can be baked into the chip GLB once verified so it persists across every future use of the chip?\n",
  "author": {
    "id": "695820315b5f1e4db2fcf602",
    "name": "Kyle Bergstedt",
    "email": "kyle@adom.inc"
  },
  "visibility": {
    "public": true
  },
  "hero": null,
  "discovery_triggers": [],
  "discovery_pitch": null,
  "metadata": {},
  "created_at": "2026-05-28T05:29:41.711Z",
  "updated_at": "2026-05-28T05:29:41.711Z",
  "sub_skills": [],
  "parent_app": null
}