# TPD2EUSB30DRTR: 2-Channel USB 3.0 TVS ESD Array (TI)

**Texas Instruments TPD2EUSB30DRTR** is a 2-channel TVS-based ESD protection array for
USB 3.0 SuperSpeed (5 Gbps) and other high-speed differential IO. Low 0.7 pF channel
capacitance and flow-through pin mapping keep it out of the way of the signal.

| | |
|---|---|
| **MPN** | TPD2EUSB30DRTR |
| **Manufacturer** | Texas Instruments |
| **Package** | SOT-3 (DRT), body 1.00 × 0.80 mm, 0.5 mm max height |
| **KiCad symbol** | `TPD2EUSB30DRTR:TPD2EUSB30DRTR` |
| **KiCad footprint** | `TPD2EUSB30DRTR:SOTFL35P100X50-3N` (SamacSys, part 417592) |
| **3D** | `tpd2eusb30drtr.glb` (page viewer) + `tpd2eusb30drtr.step` (manufacturer model) |
| **Fusion / EAGLE** | `TPD2EUSB30DRTR.lbr`, canonical hub `tpd2eusb30drtr.adom-lbr.json` |
| **Datasheet** | [SLVSAC2G](docs/TPD2EUSB30-datasheet.pdf), [ti.com](https://www.ti.com/lit/ds/symlink/tpd2eusb30.pdf) |
| **Order** | LCSC `C97502`, Mouser `595-TPD2EUSB30DRTR`, DigiKey `296-25509-2-ND` |

## Electrical (TPD2EUSB30, from SLVSAC2G)

| Parameter | Value |
|---|---|
| Channels | 2 (D+, D−), bidirectional TVS to GND |
| Reverse stand-off voltage V(RWM) | 5.5 V |
| Breakdown voltage V(BR) @ 1 mA | 7 V |
| Clamp voltage @ 1 A | 8 V |
| Dynamic resistance | 0.6 Ω typ |
| Capacitance IO→GND | 0.7 pF typ (DRT) |
| Capacitance IO→IO | 0.05 pF typ |
| IEC 61000-4-2 ESD | ±8 kV contact, ±8 kV air-gap |
| IEC 61000-4-5 surge | 5 A / 45 W peak (8/20 µs) |
| Operating temperature | −40 … 85 °C |

> The **TPD2EUSB30A** variant (same package, same footprint) drops V(RWM) to 3.6 V and
> V(BR) to 4.5 V. Use it where the protected rail never exceeds 3.6 V. This page is the
> plain **TPD2EUSB30**.

## Pinout

| Pin | Name | Type | Notes |
|---|---|---|---|
| 1 | D+ | passive | protected line |
| 2 | D− | passive | protected line |
| 3 | GND | passive | return for both TVS channels |

Flow-through mapping means the part drops straight onto a differential pair with no
stub. Place it as close to the connector as the layout allows and keep the GND pin's
via short and wide.

## Files

- `TPD2EUSB30DRTR.kicad_sym`: KiCad 9/10 symbol, 5 standard fields, 3 pins
- `SOTFL35P100X50-3N.kicad_mod`: KiCad 9 footprint, modern `(footprint …)` syntax
- `tpd2eusb30drtr.step`: manufacturer STEP. `tpd2eusb30drtr.glb`: color-preserving GLB
- `TPD2EUSB30DRTR.lbr`: EAGLE / Fusion 360 Electronics library (symbol + package + deviceset)
- `tpd2eusb30drtr.adom-lbr.json`: canonical adom-lbr hub (exports to Altium, KiCad, IntLib)
- `docs/TPD2EUSB30-datasheet.pdf`: TI SLVSAC2G, revised June 2021
- `skills/tpd2eusb30drtr-usage/SKILL.md`: how to place and wire the part

CAD came from the SamacSys bundle (part 417592). The symbol was rebuilt in the Adom house
style and the footprint converted to modern KiCad syntax.
