# LP5912Q1.1DRVRQ1: Automotive 500 mA Low-Noise LDO, 1.1 V Fixed (TI)

**Texas Instruments LP5912-Q1** is an AEC-Q100 grade-1 low-dropout linear regulator that
supplies up to 500 mA with 12 µV<sub>RMS</sub> output noise and 30 µA quiescent current,
no noise-bypass capacitor required. This page is the **1.1 V fixed** option in the 6-pin
WSON (DRV) package.

| | |
|---|---|
| **MPN** | LP5912Q1.1DRVRQ1 (tape and reel, 3000 pcs) |
| **Manufacturer** | Texas Instruments |
| **Package** | WSON-6 (DRV0006A), body 2.00 × 2.00 mm, 0.80 mm max height, 0.65 mm pitch, exposed thermal pad |
| **Part marking** | `12QH` |
| **KiCad symbol** | `LP5912Q1_1DRVRQ1:LP5912Q1.1DRVRQ1` |
| **KiCad footprint** | `LP5912Q1_1DRVRQ1:SON65P200X200X80-7N` (SamacSys, part 717743) |
| **3D** | `lp5912q1-1drvrq1.glb` (page viewer) + `lp5912q1-1drvrq1.step` (manufacturer model) |
| **Fusion / EAGLE** | `LP5912Q1_1DRVRQ1.lbr`, canonical hub `lp5912q1-1drvrq1.adom-lbr.json` |
| **Datasheet** | [SNVSAA8C](docs/LP5912-Q1-datasheet.pdf), [ti.com](https://www.ti.com/lit/ds/symlink/lp5912-q1.pdf) |
| **Order** | Mouser `595-LP5912Q1.1DRVRQ1`, DigiKey `296-46972-2-ND`, LCSC `C5220610` |

## Electrical (LP5912-Q1, from SNVSAA8C)

| Parameter | Value |
|---|---|
| Output voltage (this option) | 1.1 V fixed, ±3% over line, load and temperature |
| Output current | 0 … 500 mA |
| Input voltage | 1.6 … 6.5 V (absolute max 7 V) |
| Dropout @ 500 mA | 170 mV typ / 250 mV max (for 1.6 V ≤ V<sub>OUT</sub> < 3.3 V) |
| Output noise | 12 µV<sub>RMS</sub> (10 Hz … 100 kHz), no bypass cap |
| PSRR | 80 dB @ 100 Hz, 75 dB @ 1 kHz, 65 dB @ 10 kHz, 40 dB @ 100 kHz |
| Quiescent current | 30 µA typ (enabled, no load), 0.2 µA typ in shutdown |
| Short-circuit / current limit | 700 … 1100 mA (900 mA typ) |
| Line / load regulation | 0.8 %/V · 0.0022 %/mA |
| Load transient | ±45 mV for 5 mA ↔ 500 mA in 10 µs |
| Turn-on time | 200 µs to 95% of V<sub>OUT</sub> |
| Power-good | asserts at 94% of V<sub>OUT</sub>, releases at 90%, 140 µs delay, open-drain |
| Output auto-discharge | 100 Ω pulldown when disabled |
| Thermal shutdown | 160 °C, 15 °C hysteresis |
| Operating junction temperature | –40 … +125 °C (AEC-Q100 grade 1) |
| ESD | ±2 kV HBM (AEC-Q100-002), ±1 kV CDM |
| R<sub>θJA</sub> | 71.2 °C/W (JEDEC high-K board, 2 thermal vias) |

> **Voltage options.** LP5912-Q1 ships fixed from 0.8 V to 5.5 V; the DRV package covers
> 0.9, 1.1, 1.2, 1.5, 1.8, 2.8, 3.0 and 3.3 V as stocked orderables. Every option shares
> this symbol, footprint and 3D, so swapping voltage is a BOM change only. Devices ≥ 3.3 V
> tighten to ±2% tolerance and 95 mV typ dropout.

## Pinout

| Pin | Name | Type | Notes |
|---|---|---|---|
| 1 | OUT | power out | regulated 1.1 V, 1 µF ceramic to GND |
| 2 | NC | no connect | no internal connection; leave open or tie to GND |
| 3 | PG | open drain | power good, needs an external pullup |
| 4 | EN | input | high = on, low = off; internal 3 MΩ pulldown, 1.3 V on / 0.3 V off threshold |
| 5 | GND | power in | ground |
| 6 | IN | power in | 1.6 … 6.5 V, 1 µF ceramic to GND |
| 7 | EP | passive | exposed thermal pad; solder to a ground copper area, or leave floating; never to another potential |

## Files

- `LP5912Q1_1DRVRQ1.kicad_sym`: KiCad 9/10 symbol, 5 standard fields, 7 pins
- `SON65P200X200X80-7N.kicad_mod`: KiCad 9 footprint, modern `(footprint …)` syntax
- `lp5912q1-1drvrq1.step`: manufacturer STEP. `lp5912q1-1drvrq1.glb`: color-preserving GLB
- `LP5912Q1_1DRVRQ1.lbr`: EAGLE / Fusion 360 Electronics library (symbol + package + deviceset)
- `lp5912q1-1drvrq1.adom-lbr.json`: canonical adom-lbr hub (exports to Altium, KiCad, IntLib)
- `docs/LP5912-Q1-datasheet.pdf`: TI SNVSAA8C, revised September 2016
- `docs/symbol.svg`, `docs/footprint.svg`: rendered symbol and footprint previews
- `skills/lp5912q1-1drvrq1-usage/SKILL.md`: how to place, wire and order the part

CAD came from the SamacSys bundle (part 717743). The symbol was rebuilt in the Adom house
style and the footprint converted to modern KiCad syntax; pad geometry is unchanged from
the vendor model and sits within IPC-7351 nominal for TI's DRV0006A land pattern (signal
pads 0.35 × 0.60 mm on a 2.10 mm span, exposed pad 1.10 × 1.70 mm).
