{
  "symbolName": "NE555",
  "manufacturer": "Texas Instruments",
  "package": "PDIP-8",
  "description": "Precision timer IC for monostable, astable, and bistable timing circuits",
  "datasheetUrl": "https://www.ti.com/lit/ds/symlink/ne555.pdf",
  "pinCount": 8,
  "pinDescriptions": {
    "GND": "Ground reference. Connect to circuit ground plane with short, low-impedance trace.",
    "VCC": "Positive supply voltage input. Operating range 4.5V to 16V. Bypass with 100nF ceramic capacitor close to pin.",
    "TRIG": "Trigger input. A negative pulse below 1/3 VCC initiates the timing cycle and sets the output high. Input impedance is approximately 10MΩ.",
    "THRES": "Threshold input. When voltage exceeds 2/3 VCC, the timing cycle ends and the output goes low. Typically connected to the external RC timing network.",
    "DISCH": "Discharge output. Open-collector transistor output that discharges the external timing capacitor when the output goes low. Connected between VCC and the timing capacitor through the timing resistor.",
    "OUT": "Timer output. Drives high (near VCC) or low (near GND) with up to 200mA sink/source capability. Rise and fall times are approximately 100ns.",
    "RESET": "Active-low reset input. Pulling below 0.7V forces output low and overrides all other inputs. Tie to VCC through a 10kΩ resistor if not used.",
    "CTRL": "Control voltage input. Provides direct access to the internal 2/3 VCC comparator reference. Bypass with 10nF capacitor to ground for noise immunity, or drive externally to modulate timing."
  },
  "groupDescriptions": {
    "POWER": "Supply pins. VCC accepts 4.5V–16V. Bypass VCC with 100nF ceramic close to the pin. GND is the reference for all internal comparators and the output stage.",
    "TIMING": "Timing network interface. TRIG starts the cycle (falling edge below 1/3 VCC), THRES ends it (rising above 2/3 VCC), and DISCH resets the external RC capacitor. Together they set the output pulse width: t = 1.1 × R × C.",
    "OUTPUT": "Push-pull output capable of sourcing or sinking up to 200mA. Drives TTL and CMOS loads directly. Output swings within ~1.5V of each rail.",
    "CONTROL": "RESET overrides all timing and forces output low. CTRL provides access to the internal voltage divider reference (2/3 VCC) for modulation or improved noise rejection."
  }
}