LAN7800
Microchip TechnologyUSB 3.1 → GbE
Single-chip SuperSpeed USB 3.1 Gen 1 to 10/100/1000 Gigabit Ethernet bridge controller. Folds a USB 3.1 device controller and PHY, a Gigabit Ethernet MAC, and a Gigabit PHY with HP Auto-MDIX into one 48-pin QFN. Configured via on-chip OTP (no external EEPROM); Energy Efficient Ethernet, Wake-on-LAN and NetDetach; drivers for Windows, Linux, macOS, uBoot, UEFI, PXE and FreeBSD.
Package QFN-48Body 7×7 / 6×6 mmPitch 0.5 / 0.4 mm
Pins 48 + EPHost USB 3.1 Gen 1Link 5 Gbps
The interactive symbol and footprint viewers at the top of the page are rendered from the CAD shipped here. Use the toggle at the top-right of the PCB Footprint card to switch between the QFN 7×7 mm (Y9X) and QFN 6×6 mm (VSX) packages. Pin 1 is the square pad. Downloadable KiCad / Fusion / Altium libraries, STEP, GLB and the datasheet are on the Files tab.
Symbol & footprint
Schematic symbol — hover a pin for its datasheet description
PCB footprint — use the toggle at the top-right to switch QFN 7×7 (Y9X) / QFN 6×6 (VSX)
At a glance
Host interface
USB 3.1 Gen 1
SuperSpeed device controller + PHY
Link speed
5 Gbps
SS · 480 Mbps HS · 12 Mbps FS
Network
10 / 100 / 1000
Gigabit Ethernet MAC + PHY, Auto-MDIX
Package
QFN-48
7×7 mm (Y9X) · 6×6 mm (VSX)
Config
On-chip OTP
No external EEPROM · EEE + WoL
I/O
8 GPIO
Flexible LEDs · 1.8–3.3 V supply
Specifications
Host interfaceUSB 3.1 Gen 1 (SuperSpeed, 5 Gbps)
Network10 / 100 / 1000 Mbps Ethernet, IEEE 802.3/3u/3ab/3az
Integrated PHYGigabit Ethernet PHY with HP Auto-MDIX, auto-negotiation
USB speedsSS 5 Gbps / HS 480 Mbps / FS 12 Mbps, 4 endpoints
ConfigurationOn-chip OTP memory (no external EEPROM)
Low powerEnergy Efficient Ethernet (802.3az), Wake-on-LAN, NetDetach
GPIO8, with flexible link/activity LEDs
I/O supply1.8 to 3.3 V (variable)
Offloads802.1q VLAN, 9 KB jumbo frames, IPv4/IPv6/TCP/UDP checksum, 32 wake-up patterns
TemperatureCommercial 0 to +70 °C / Industrial −40 to +85 °C
Pin map — 48 signals + exposed pad, grouped by function
Ethernet PHY8
| 1 | TR0P | Gigabit Ethernet MDI pair 0 (+) |
| 2 | TR0N | Gigabit Ethernet MDI pair 0 (−) |
| 4 | TR1P | Gigabit Ethernet MDI pair 1 (+) |
| 5 | TR1N | Gigabit Ethernet MDI pair 1 (−) |
| 7 | TR2P | Gigabit Ethernet MDI pair 2 (+) |
| 8 | TR2N | Gigabit Ethernet MDI pair 2 (−) |
| 10 | TR3P | Gigabit Ethernet MDI pair 3 (+) |
| 11 | TR3N | Gigabit Ethernet MDI pair 3 (−) |
USB 3.1 SS4
| 28 | USB3_TXDP | SuperSpeed transmit + |
| 29 | USB3_TXDM | SuperSpeed transmit − |
| 31 | USB3_RXDP | SuperSpeed receive + |
| 32 | USB3_RXDM | SuperSpeed receive − |
USB 2.02
| 26 | USB2_DP | USB 2.0 HS/FS data + |
| 27 | USB2_DM | USB 2.0 HS/FS data − |
Clock2
| 40 | XI | 25 MHz crystal / external clock input |
| 41 | XO | 25 MHz crystal output |
Analog3
| 37 | USBRBIAS | USB bias — external reference resistor |
| 47 | REF_REXT | PHY bias — external reference resistor to GND |
| 48 | REF_FILT | PHY internal-regulator filter |
Config / GPIO4
| 16 | EECS/GPIO0 | OTP/EEPROM chip-select (SPI) / GPIO0 |
| 17 | EEDI/GPIO1 | OTP/EEPROM data-in (SPI) / GPIO1 |
| 18 | EEDO/LED0/GPIO2 | OTP/EEPROM data-out (SPI) / LED0 / GPIO2 |
| 19 | EECLK/LED1/GPIO3 | OTP/EEPROM clock (SPI) / LED1 / GPIO3 |
LED / GPIO4
| 22 | PME_N/GPIO4 | Power-management-event out / GPIO4 |
| 24 | SUSPEND_N/LED2/GPIO5 | Suspend indicator / LED2 / GPIO5 |
| 33 | LED3/GPIO6 | Link/activity LED (LED3/GPIO6) |
| 43 | PME_MODE/GPIO7 | PME mode strap / GPIO7 |
Control3
| 23 | VBUS_DET | USB VBUS detect input |
| 34 | TEST | Factory test — connect per datasheet |
| 35 | RESET_N/PME_CLEAR | Active-low reset, muxed with PME clear |
Power18
| 3 | VDD25A | 2.5 V analog |
| 6 | VDD25A | 2.5 V analog |
| 9 | VDD25A | 2.5 V analog |
| 12 | VDD25A | 2.5 V analog |
| 13 | VDD12_SW_OUT | 1.2 V switcher out |
| 14 | VDD_SW_IN | Switcher in |
| 15 | VDD12_SW_FB | 1.2 V switcher feedback |
| 20 | VDDVARIO | Variable I/O (1.8–3.3 V) |
| 21 | VDD12CORE | 1.2 V digital core |
| 25 | VDD12A | 1.2 V analog |
| 30 | VDD12A | 1.2 V analog |
| 36 | VDDVARIO | Variable I/O (1.8–3.3 V) |
| 38 | VDD33A | 3.3 V analog |
| 39 | VDDVARIO | Variable I/O (1.8–3.3 V) |
| 42 | VDD12CORE | 1.2 V digital core |
| 44 | VDD12A | 1.2 V analog |
| 45 | VDD25_REG_OUT | 2.5 V regulator out |
| 46 | VDD33_REG_IN | 3.3 V regulator in |
Ground1
| 49 | VSS | Exposed thermal pad — tie to GND via field |
Component variants
Eight orderable part numbers, all identical LAN7800 silicon — differing only in package size, temperature grade and packaging. Order code: LAN7800 [T] [-I] / {Y9X | VSX} — T = Tape & Reel, -I = Industrial, Y9X = 7×7 mm, VSX = 6×6 mm.
QFN 7×7 mmY9X · default
0.5 mm pitch · 5.3 × 5.3 mm exposed pad · 1.0 mm body
| Order code | Packaging | Temperature |
|---|
LAN7800/Y9X | Tray | Commercial 0…+70 °C |
LAN7800T/Y9X | Tape & Reel | Commercial 0…+70 °C |
LAN7800-I/Y9X | Tray | Industrial −40…+85 °C |
LAN7800T-I/Y9X | Tape & Reel | Industrial −40…+85 °C |
QFN 6×6 mmVSX
0.4 mm pitch · 4.3 × 4.3 mm exposed pad · 0.9 mm body
| Order code | Packaging | Temperature |
|---|
LAN7800/VSX | Tray | Commercial 0…+70 °C |
LAN7800T/VSX | Tape & Reel | Commercial 0…+70 °C |
LAN7800-I/VSX | Tray | Industrial −40…+85 °C |
LAN7800T-I/VSX | Tape & Reel | Industrial −40…+85 °C |
Assets
CAD for every major EDA tool, generated from the canonical adom-lbr JSON so symbol, footprint and 3D stay in sync.
Applications
Provenance
- Datasheet: Microchip LAN7800 (DS00001992)
- Symbol, QFN 7×7 (Y9X) footprint, STEP + GLB: Adom library, from the canonical adom-lbr JSON.
- QFN 6×6 (VSX) footprint: KiCad official library (
QFN-48-1EP_6x6mm_P0.4mm_EP4.3x4.3mm).
- Fusion and Altium libraries generated from the adom-lbr JSON with
adom-lbr.