ZTP7193KT

@@ -26,19 +26,21 @@       "model_3d_step": "ztp7193kt.step",       "lbr": "ztp7193kt.lbr"     },-    "distributor_links": {},+    "distributor_links": {+      "lcsc": "C481283"+    },     "pins": [       {         "number": "1",         "name": "GND",         "type": "power_in",-        "description": "Device ground return. Connect to a large copper ground pour for thermal dissipation (θJA = 100°C/W) and low-impedance return of the switching currents."+        "description": "Device ground return. Connect to a large copper ground pour for thermal dissipation (\u03b8JA = 100\u00b0C/W) and low-impedance return of the switching currents."       },       {         "number": "2",         "name": "SW",         "type": "output",-        "description": "Power switching node - output of the internal high-side and low-side N-channel MOSFETs. Connect to the external inductor of the LC output filter. A capacitor from SW to BOOT powers the high-side gate driver. Rated −0.3V to VIN+0.3V (−5V to 21V for <10ns transients)."+        "description": "Power switching node - output of the internal high-side and low-side N-channel MOSFETs. Connect to the external inductor of the LC output filter. A capacitor from SW to BOOT powers the high-side gate driver. Rated \u22120.3V to VIN+0.3V (\u22125V to 21V for <10ns transients)."       },       {         "number": "3",@@ -50,19 +52,19 @@         "number": "4",         "name": "FB",         "type": "input",-        "description": "Feedback input to the internal error amplifier. Drive with a resistive divider from VOUT; regulation threshold is 0.765V (typ). Over-voltage comparator trips at 0.96V (≈20% above nominal), turning the high-side switch off."+        "description": "Feedback input to the internal error amplifier. Drive with a resistive divider from VOUT; regulation threshold is 0.765V (typ). Over-voltage comparator trips at 0.96V (\u224820% above nominal), turning the high-side switch off."       },       {         "number": "5",         "name": "EN",         "type": "input",-        "description": "Enable digital input. Drive high (rising threshold 1.22V typ) to enable the regulator, low (falling threshold 1.12V typ) to shut it down (IQ ≈ 3µA). Pull up with a 100kΩ resistor to IN for automatic startup. Absolute max 6V."+        "description": "Enable digital input. Drive high (rising threshold 1.22V typ) to enable the regulator, low (falling threshold 1.12V typ) to shut it down (IQ \u2248 3\u00b5A). Pull up with a 100k\u03a9 resistor to IN for automatic startup. Absolute max 6V."       },       {         "number": "6",         "name": "BOOT",         "type": "passive",-        "description": "High-side gate-drive bootstrap input. Connect a 0.1µF (or greater) capacitor from SW to BOOT to develop the gate-drive supply for the internal high-side N-channel MOSFET. Charged from the internal 5V rail when SW is low. Rated VSW−0.3V to VSW+6V."+        "description": "High-side gate-drive bootstrap input. Connect a 0.1\u00b5F (or greater) capacitor from SW to BOOT to develop the gate-drive supply for the internal high-side N-channel MOSFET. Charged from the internal 5V rail when SW is low. Rated VSW\u22120.3V to VSW+6V."       }     ],     "provenance": {

@@ -60,6 +60,18 @@   <smd name="4" x="1.1375" y="-0.9500" dx="1.3250" dy="0.6000" layer="1"/>   <smd name="5" x="1.1375" y="-0.0000" dx="1.3250" dy="0.6000" layer="1"/>   <smd name="6" x="1.1375" y="0.9500" dx="1.3250" dy="0.6000" layer="1"/>+  <polygon width="0.1200" layer="21">+    <vertex x="-1.4500" y="1.5100"/>+    <vertex x="-1.6900" y="1.8400"/>+    <vertex x="-1.2100" y="1.8400"/>+  </polygon>+  <polygon width="0.1000" layer="51">+    <vertex x="-0.4000" y="1.4500"/>+    <vertex x="0.8000" y="1.4500"/>+    <vertex x="0.8000" y="-1.4500"/>+    <vertex x="-0.8000" y="-1.4500"/>+    <vertex x="-0.8000" y="1.0500"/>+  </polygon>   <wire x1="-0.9100" y1="1.5600" x2="0.9100" y2="1.5600" width="0.1200" layer="21"/>   <wire x1="-0.9100" y1="1.5100" x2="-0.9100" y2="1.5600" width="0.1200" layer="21"/>   <wire x1="-0.9100" y1="-1.5600" x2="-0.9100" y2="-1.5100" width="0.1200" layer="21"/>@@ -68,7 +80,7 @@   <wire x1="0.9100" y1="-1.5600" x2="-0.9100" y2="-1.5600" width="0.1200" layer="21"/>   <text x="0" y="2.212" size="1.27" layer="25" align="bottom-center">&gt;NAME</text>   <text x="0" y="-2.212" size="1.27" layer="27" align="top-center">&gt;VALUE</text>-<!--adom-pin1--><polygon width="0.0500" layer="21"><vertex x="-1.4500" y="1.5100"/><vertex x="-1.6900" y="1.8400"/><vertex x="-1.2100" y="1.8400"/></polygon></package>+</package> </packages> <symbols> <symbol name="ZTP7193KT">@@ -102,7 +114,13 @@         <connect gate="G$1" pin="EN" pad="5"/>         <connect gate="G$1" pin="FB" pad="4"/>       </connects>-      <technologies><technology name=""/></technologies>+      <technologies>+        <technology name="">+          <attribute name="MPN" value="ZTP7193KT" constant="no"/>+          <attribute name="MANUFACTURER" value="ZILLTEK" constant="no"/>+          <attribute name="LCSC_PN" value="C481283" constant="no"/>+        </technology>+      </technologies>     </device>   </devices> </deviceset>