YD3082EESA

@@ -0,0 +1,47 @@+# YD3082EESA++**GATEMODE** · RS-485 / RS-422 ICs · SOP-8++YD3082EESA from GATEMODE, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | RO | output | Receiver Output. When /RE is low: if (A-B) ≥ -50mV, RO is logic high; if (A-B) ≤ -200mV, RO is logic low. VOH ≥ VCC-1.5V at IO=-4mA; VOL ≤ 0.4V at IO=1mA. |+| 2 | /RE | input | Receiver Output Enable (active low). Drive /RE low to enable RO; drive /RE high to place RO in high-impedance. Driving /RE high and DE low enters low-power shutdown mode (ISHDN typ 0.1µA). |+| 3 | DE | input | Driver Output Enable (active high). Drive DE high to enable the A/B driver outputs; when DE is low, driver outputs are high-impedance. Driving /RE high and DE low enters low-power shutdown mode. |+| 4 | DI | input | Driver Input. With DE high, a low on DI forces A (non-inverting) low and B (inverting) high; a high on DI forces A high and B low. VIH=2.0V min, VIL=0.8V max, 100mV typical hysteresis. |+| 5 | GND | power_in | Ground reference for the device. |+| 6 | A | bidirectional | Non-inverting Receiver Input and Non-inverting Driver Output (RS-485/RS-422 differential bus line A). ±15kV HBM ESD protected. Receiver input voltage ±13V, driver output voltage ±13V, receiver input impedance 96kΩ (1/8 unit load). |+| 7 | B | bidirectional | Inverting Receiver Input and Inverting Driver Output (RS-485/RS-422 differential bus line B). ±15kV HBM ESD protected. Receiver input voltage ±13V, driver output voltage ±13V, receiver input impedance 96kΩ (1/8 unit load). |+| 8 | VCC | power_in | Positive supply, VCC = 3.0~5.5V. Bypass VCC to GND with a 0.1µF ceramic capacitor. Absolute maximum +7V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | GATEMODE |+| Package | SOP-8 |+| Category | Interface |+| Pins | 8 |++## Ordering variants++- `YD3082EESAESA`++## CAD (KiCad official)++- Symbol: `YD3082EESA`+- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`+- 3D model: SOP-8 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [GATEMODE datasheet](docs/yd3082eesa-datasheet.pdf) (12 pp, sha256 `3e495c65364195a4`, retrieved 2026-08-17, tier: lcsc)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/yd3082eesa-datasheet.pdf)

@@ -0,0 +1,34 @@+{+  "slug": "yd3082eesa",+  "version": "0.1.0",+  "type": "component",+  "description": "GATEMODE RS-485 / RS-422 ICs, SOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "interface",+    "yd3082eesa"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "yd3082eesa.kicad_sym",+    "yd3082eesa.kicad_mod",+    "yd3082eesa.glb",+    "yd3082eesa.step",+    "yd3082eesa.lbr",+    "docs/hero.png",+    "docs/yd3082eesa-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "visibility": "public",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file